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Recent content by shashi_reddy21

  1. S

    Looking for flow pack manual

    flow pack manual Hello Can any one share flowpack manual ,it will will be very usefull for me Regards
  2. S

    When do we do clock tree synthesis?

    When do we do clock tree synthesis?
  3. S

    What is the difference between syn reset and asyn reset in Verilog?

    whats is the difference between syn reset and asyreset in verilog
  4. S

    What is the latest C++ compiler you recommend?

    borland turbo c++ compiler 3.0 64 bit Hi, The latest c++ compiler is g++343
  5. S

    SystemC examples for behavioral and RTL level

    Hi any one can get me a systemc example at different level of abstraction 1.behavioral 2.SystemC RTL level l
  6. S

    Setup ddd debugger for systemC

    Hi..for debugging ,go to Vista fa SystemC IDE from Summit design.its has gdb integrated,it has its own waveform,TLM viewer.I guess it solves ur problems Regards shashi
  7. S

    What are the course contents of system programming ?

    system programming.... Hi... The system programming basically a sysem level design like designing of device drivers.......mosly done in C... Regards shashi
  8. S

    about SOC design language:systemc

    Hi .. you can download OSCI simulation kernal from systemc.org ,which is a free tool.if u want commecial tools i can get u more info ..
  9. S

    What are the course contents of system programming ?

    Re: system programming.... hi system programming mainly compraises of C,C++ and linux,
  10. S

    How to simulate a multiplier (frequency doubler) ?

    Re: SIMULATION OF MULTIPLIER compile all the small modules and compile the top module then simulate the to[p module
  11. S

    Consider a 2:1 mux , what will output if sel is"x"

    2:1 mux, select is x hi if select is x ,then the output should be x only
  12. S

    Synthesis of a Verilog code

    with xilinx ise pack u can not syntheize.u nedd to have a synthesis tool from synopsys or from synplypro .which are costly to buy.
  13. S

    Help me choose a field for major project (M.E. in VLSI)

    Re: idea for project The first choice is better as u can learn interfacing concepts as ur using both vlsi and DSP and 3rd one also good ...u can explore in to analog design which is having good opeonings now
  14. S

    Looking for beginner books/tools for VLSI design

    Re: VLSI study VERILOG by samir palnitkar ..then u will be knowing about VLSI
  15. S

    What is FPGA and what is it for?

    Re: FPGA FPGA:Field Programmable Grip Array nothing but array of gates in achip ,which u can program according to your need ,u can program them using verilog and u can implement using fpga kit after synthesis. Added after 13 seconds: FPGA:Field Programmable Grid Array nothing but array of...
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