What is the difference between syn reset and asyn reset in Verilog?

[shashi_reddy21]

whats is the difference between syn reset and asyreset in verilog

 

[ankit12345]

reset -syn and asyn

If reset can be done at any time independent of clock ...its async reset.
If reset is dependent on clk....than its sync.
sync reset looks like data signal......but not like control signal to synthesis tool........
asyncreset is porne to glitches and may lead to metastability.....................

http://www.sunburst-design.com/papers/

check for the papers on this topic........

 

[vinod_g]

Re: reset -syn and asyn

in synchronus reset ,the reset signal is read at the clk edge ,but in the asynchronuous reset independent of the clk ..........

in verilog if u write reset and clk in sensitivity list it is asyn reset ,only clk means sync reset

 

[sivakumar_tumma]

Re: reset -syn and asyn

sync reset works wirt respect to clock, where as asyn reset work independent of clok...

in sync reset u can preserve data, where as the data may lost in asyn reset it will reset outputs immediately whether it is sved or not.....