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Recent content by sharath666

  1. S

    passing the data safely from fast domain to slow domain in synchronous design

    If the clocks are synchronous then a dual port RAM should do. You need to keep in mind the write burst behaviour and accordingly determine the depth of the RAM.
  2. S

    PHY, SerdEs, PLL in FPGA

    Which board are you referring to? U will need to check the board datasheet or check it on the xilinx website. This is too general a question..
  3. S

    Primetime Environment setup

    lsi_10k.db is not in the current path. Specify the correct path for that file. Fix this first and then see whether you get the 2nd error.
  4. S

    Choosing between MIG IP core and AXI IP core

    A MIG core is a memory controller while an AXI core is a bus interface core. How can you not find a significant difference between the two?
  5. S

    [SOLVED] TCL testbench in Modelsim

    Well, you can type it first and then copy them into a .do file and then run the .do file.....For a big design you will have to type a lot of commands. Not so for a small design..
  6. S

    porting of constraints for synthesis at the top?

    You might have to change the port names in the constraints. Replace the port names of the inner modules with the port names of the top module. You will also need to change the hierarchies within the constraints.
  7. S

    [SOLVED] TCL testbench in Modelsim

    This approach works fine and is very convenient if you are testing a small design. For big designs like the ones which you are testing, it is not a good idea. Using HDL is a better approach.
  8. S

    writing and reading in two port memory.

    What I am aware of is that when the write and read addresses are same you get back the data which was already there in that location for the read and the new write data will go and overwrite this existing data.
  9. S

    Delayed assign in Verilog

    I agree with you. The result should be the same if your intention is to generate clocks.
  10. S

    Delayed assign in Verilog

    1. It is legal. (You wait for 5 time units, invert value of a and assign it to a) 2. This is different. you are modelling transport delay here. 3.Define the timescale accordingly..
  11. S

    Reading byte by byte from a register

    If target_reg has to be written to a FIFO then you can do only a single write every cycle which means a single read of 8 bits every cycle. You will not need the for loop in that case. You will run a counter for 16 cycles and then write a case statement (using this counter) to index source_reg...
  12. S

    Multi cycle path of N clock cycles

    Type "set_multicycle_path --help" at the command prompt. It will display the command syntax for you. If I remember right, there are options like -setup and -hold to specify the setup and hold options..
  13. S

    Multi cycle path of N clock cycles

    I suppose you are using some tool like Dc compiler and you want to specify a multicycle path constraint for a design...right ???
  14. S

    Multi cycle path of N clock cycles

    Check the command guide of the tool you are using....
  15. S

    Async Reset Implementation -> Coding Styles

    The former case does not use a reset while the latter case uses an asynchronous reset.
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