passing the data safely from fast domain to slow domain in synchronous design

[sun_ray]

Data is coming at 200 MHz and is being read at 100 MHz. The width of the data is 4 bit. Can we put a dual port RAM to transfer the data from 200 MHz domain to 100 MHz domain. Here all the clocks are synchronous throughout the design?

 

[sharath666]

If the clocks are synchronous then a dual port RAM should do. You need to keep in mind the write burst behaviour and accordingly determine the depth of the RAM.

 

[KlausST]

Hi,

I'm not sure if the dual port is the best solution. I tend to a FIFO solution.

If you are going to the full 200M datarate, then you should consider to read two x 4 bit (or more) every 100MHz clock, else you run into FIFO overflow.

In any case you need to be able to read (at the 100MHz domain) at least the same ammount of data than you write in the 200MHz domain.

200MHz x 4 bits = 800MBits/s = 100MHz x 8 bits.

Klaus

 

[FvM]

Questions of data rate or read/write address sequence are in fact involved, but apparently the OP has no problems in this regard, so why should we read them into this question?

Dual port RAM can be also used to transfer data between asynchronous clock domains, as long as overlapping accesses to the same memory cell are avoided by suitable means.

 

[KlausST]

Hi,

Since a dual port ram has limited size, one needs a circular addressing. On both sides.

With synchronous clocks the max datarate is when the data is stored at every second clock cycle of the 200MHz clock.

In my eyes the dual port RAM solution only works when
* there is a continous datastream
* with a fixed, known datarate.(integer division of 100MHz)
Else you need extra sync signals to transmit from one domain to the other.
But for sure it is possible.

***
With the FIFO, there are some benefits:
* works with unsynchronous clock also
* syncing is automatically made with the FIFO typical status signals
* both writing and reading can work with "gaps" in the datastream. ( bulk write or bulk read)
* status signals prevent underflow
* status signals show loss of data

Klaus

 

[FvM]

The original post doesn't talk about a continuous data stream. "Data is coming at 200 MHz" could mean a continuous data stream (which doesn't make sense if it's read at half the rate) or just define the clock rate for arbitrary write accesses. Without additional info, I prefer the second meaning.

I take it as granted that some posters don't like to ask clear questions.