writing and reading in two port memory.

[sun_ray]

There is a two port memory. Write will happen continuously in every clock cycles and read will happen in every clock cycles in this memory continuously. Now there can be situation when read address is same as write address. In that situation read data will be x at the read address where read address and write address are same. How to take care of such a situation so that when write and read address are equal reading and writing happens properly? What logic to add so that when write and read address are equal reading and writing happens properly?

 

[sharath666]

What I am aware of is that when the write and read addresses are same you get back the data which was already there in that location for the read and the new write data will go and overwrite this existing data.

 

[FvM]

1. You apparently assume a single clock dual port memory, but you didn't say.
2. You also didn't say what "happens properly" means for you. In a single clock dual port memory, I would expect the behavior described by sharath666 to happen naturally, without additional logic.

 

[sun_ray]

1. You apparently assume a single clock dual port memory, but you didn't say.

It is a two port memory where reading and writing happens in every clock.

2. You also didn't say what "happens properly" means for you.

The problem with two port memory is that there can be situation when read address is same as write address. In that situation read data will be x at the read address where read address and write address are same. So we do not read the proper data at that read address and we read 'x'. Here happens properly means we read the correct data from that address instead of X and write data at that address correctly.

- - - Updated - - -

What I am aware of is that when the write and read addresses are same you get back the data which was already there in that location for the read and the new write data will go and overwrite this existing data.

How can you do in a single clock cycle where read and write address is same? How in same clock cycle you will read first and then write?

 

[KlausST]

Hi,

usually you should avoid situations where read and write access both the same address.
There is always an uncertainty what data you get back.
Often this is made with some RAM banks. One is written at a time, one is read at a time, and a third is free for th next bank switching. The three banks are rotating continously.

I recommend something like an access arbitration.

Klaus

 

[sun_ray]

Hi,

usually you should avoid situations where read and write access both the same address.
There is always an uncertainty what data you get back.
Often this is made with some RAM banks. One is written at a time, one is read at a time, and a third is free for th next bank switching. The three banks are rotating continously.

I recommend something like an access arbitration.

Klaus

Can you please describe in more detail that how the RAM bank looks. What will be the sizes of the RAM bank? How many RAM banks will be necessary? How will these RAM bank interact with the two port memory so that the problem of reading and writing at the same address is removed? Can you please draw a diagram if necessary?

 

[FvM]

In a single clock dual port memory, there's a well defined timing relation between write and read actions and the memory can be designed to read the old data while new data is written in the same cycle. Similar to a register that is written in one clock cycle while the old data is "copied" to a differet signal.

E.g. Altera block ram IP has a parameter READ_DURING_WRITE_MODE_MIXED_PORTS which can be set to OLD_DATA. There are some prerequisites for implementing the behaviour, e.g. registered outputs and addresses.

 

[sun_ray]

Let us see what KlausST replies.

 

[KlausST]

Hi,

in a dual port memory both sides accesses are asynchronous to each other.
Let´s assume two devices A and B access the same dual port memory.
Even if inside the dual port memory (could be inside an FPGA) there is a common clock to control the access to the RAM cells, one can not be sure if one reads the "old" or the "new" value.

So one solution is to define banks (or blocks). Every block access can be seen from each device as an atomic access.

An example of an application: profibus interface.
(three buffers A, B,C for one direction)
The profibus master (SPS, PLC control) sends data packets to the profibus receiver IC. It stores it´s data in a free block X, during transmission X is marked as "receiving", after receiving the complete packet it is marked as "valid".
(now consider the microcontroller doesn´t read this packet)
If a new packet is received it is stored in a free block Y, during write it is marked as "receiving" afterwards as "valid", and the same time X is marked as free.
(still the microcontroller doesn´t read)
If now a new packet is received it is stored in a free block X, during write it is marked as "receiving"
Now consider the microcontroller wants to read. It looks for the "valid" packet. It is Y. The microcontroller marks it as "reading".
The receive of the packet finishes... X is marked as "valid"
A new packet is received. Data is transferred to free block Z. ... and so on.

At least three blocks are necessary. Each can be marked as "free", "valid", "receiving (data from PLC)", and "reading (data by microcontroller)"

This ensures that all the data within one block is consitent.
The PLC may send 40 packets per second
The microcontroller may asynchronously read with a rate of one packet per second

Klaus

 

[FvM]

Does posting the thread in the ASIC section imply that you want to design the gate level logic of a dual port RAM with "read old data on simultaneous RW" feature? Or is it about the functionality of existing block RAM IP?

Even if inside the dual port memory (could be inside an FPGA) there is a common clock to control the access to the RAM cells, one can not be sure if one reads the "old" or the "new" value.

Actual IP specification tells different...