Async Reset Implementation -> Coding Styles

[ivlsi]

Hi All,

What's the difference in the following codes implementation (two pieces of code)?
Let's assume that the reset (rstn) happens only once... So, is there a difference in the code implementation/behavior?

----------------------------------------------------------------------
signal Q : std_logic := '0';
process (clk) is
  begin
      if rising_edge(clk) then  
         Q <= IN;
      end if;
   end process;

----------------------------------------------------------------------
 signal Q : std_logic;
process (clk,rstn) is
  begin
      if falling_edge(rstn) then  
         Q <= '0';
      elsif rising_edge(clk) then  
         Q <= IN;
      end if;
      end if;
   end process;

Thank you!

 

[sharath666]

The former case does not use a reset while the latter case uses an asynchronous reset.

 

[maxbjurling]

Be aware that the first code snippet may cause differences between simulation and reality, since the initialization statement

signal Q : std_logic := '0';

will not be synthesized. This is a dangerous coding style which may easily cause bugs.

 

[FvM]

I don't understand the question. The first snippet has no reset action at all. Also the second code does not implement an asynchronous reset. Instead it has two edge sensitive conditions which aren't synthesizable in usual programmable logic hardware.

Contradicting maxbjurling, it should be noticed that most logic synthesis tool do synthesize initialization statements as power-on reset. But it's no exactly the same as an external reset input because you can't control its timing, it's e.g. not possible to release it synchronous to a clock.

 

[wtr]

What you probably want for the first case is

---

Code VHDL - [expand]
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process (clk) is
  begin
      if rising_edge(clk) then
        if rstn = '0' then
           Q <= '0';
        else   
          Q <= IN;
        end if;
     end if;
end process;

---

Also second case has two end ifs

 

[ads-ee]

What you probably want for the first case is

---

Code VHDL - [expand]
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process (clk) is
  begin
      if rising_edge(clk) then
        if rstn = '0' then
           Q <= '0';
        else   
          Q <= IN;
        end if;
     end if;
end process;

---

Also second case has two end ifs

ivlsi, this code represents a synchronous reset, not an asynchronous reset, so that is a major difference.

The asynchronous version is written typically like this:

---

Code VHDL - [expand]
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process (clk, rstn) is
  begin
      if rstn = '0' then
          Q <= '0';
      elsif rising_edge(clk) then
          Q <= IN;
      end if;
end process;

---

and behaves differently than the previous code posted by wesleytaylor.

 

[maxbjurling]

FvM, this may be true for FPGA tools but ASIC synthesis tools ignore initial assignments. And this thread is in the "ASIC Design Methodologies and Tools" section.