Choosing between MIG IP core and AXI IP core

[Sunayana Chakradhar]

Hello,

I have to interface a parallel asynchronous SRAM with my ZC7020 FPGA. I will be writing and reading data (approx:9MB) to and from the SRAM to the FPGA. I have to choose between MIG IP core and AXI EMC v3 IP core for my application. I am not finding any significant difference between the two on the internet. Somebody please explain me the difference between these two IP cores and which one should i choose for my application?

 

[sharath666]

A MIG core is a memory controller while an AXI core is a bus interface core. How can you not find a significant difference between the two?

 

[dpaul]

Hello,
I have to choose between MIG IP core and AXI EMC v3 IP core for my application. I am not finding any significant difference between the two on the internet. Somebody please explain me the difference between these two IP cores and which one should i choose for my application?

Can you provide the PDF file names from Xilinx?
e.g.- The AXI EMC v3 IP spec is defined by the file pg100-axi-emc.pdf (AXI EMC v3.0, LogiCORE IP Product Guide)
On searching with the keyword "MIG IP core" I found a doc named ug086.pdf - Memory Interface Solutions.

Are the ones above you are referring to?

In order to clarify yourself and for our benefit, can you also very briefly say (as per your understanding) what are the functions of the MIG IP core and AXI EMC v3 IP core?

 

[ads-ee]

I am not finding any significant difference between the two on the internet. Somebody please explain me the difference between these two IP cores and which one should i choose for my application?

What do you mean there is "no significant difference"? The two cores are for different types of memory! The following information can be found for the cores in their respective user guides and the summary page on Xilinx's website.

MIG for DDR2, DDR3, QDR-II, RLDRAM, etc.

EMC for SRAM, ZBT, and other similar SRAM like interfaces.

So if you are using SRAM then you use EMC not the MIG. MIG with the exception of QDR-II is for Dynamic RAM (i.e. the kind of RAM that needs to be refreshed) QDR-II is the exception because of the data rates it can support require the same IDELAY/ODELAY PHASOR support to dial in the sampling eye.