Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
We have urgent multiple openings for Physical design engineers (2+ years exp.) at Wafer Space. If anybody looking for a change, please forward resume to saikatt.sarkar@gmail.com.
Thanks
saikat
saikatt.sarkar@gmail.com.
Hi,
I need to build a RGMII to SGMII bridge. I have used the "rgmii_v2_0_if.vhd" file available in one of the Ethernet MAC core source files generated from LogiCOre. But the data capturing is somehow not proper. For example, if there are 3 consecutive bytes, the receiver interface collects the...
Re: howto control UART as a component in a system written in
you need to design a state machine which will take the data from the UART module and then put it into the SRAM.
first of all, which PHY chip are you using?
are you using Xilinx MAC? it has an host interface which will help you to connect with PHY chip.
how do you write to PHY register? if you used MDIO for that, then you can surely read the PHY registers using MDIO.
you need to apply proper settings in...
DDR on ML402 problem
Has anyone been able to get the ML402's DDR SDRAM running with a
MIG-generated DDR controller, as opposed to the EDK PLB/OPB DDR controller? I have generated DDR SDRAM interface core from MIG, but unable to generate bit file with the pin locking as inplemented in the board...
iserdes
I am using an ISERDES for high speed sampling of an input signal. I have configured ISERDES in NETWORKING and DDR mode. The internal parallel data bits width of the ISERDES is configured as 8 bits wide (so the internal clock frequency should be 4 times less than the input clock...
vertex 4 serdes
I have a specific query regarding the usage of SelectIO/RocketIO SERDES features available in Vertex 4. I have gone through the Vertex 4 user guide and quite a few application notes related to them. What I have understood that these features are mainly applicable for high speed...
Re: clock in fpga
Is it possible to generate 500MHz internal clock in Vertex 4 using DCM, where input clock frequency is 50MHz? I have tried the same, but DCM is not allowing more than 350MHz output clock. How can I achieve this? Is there any different clocking methodology?
What is the...
Is it possible to generate 500MHz internal clock in Vertex 4 using DCM, where input clock frequency is 50MHz? I have tried the same, but DCM is not allowing more than 350MHz output clock. How can I achieve this? Is there any different clocking methodology?
What is the clocking strategy for...
OK, I like to ask the question in a different way with an example.
Lets say, there is an external 64 bit bus (LVTTL) whose maximum frequency is 100MHz and it is connected to 64 digital I/O pins of Vertex 4. I need to sample the bus at every 2ns (i.e. @ 500MHz clock), and want to dump the...
What is the maximum possible frequency of a signal that can be properly handled by Vertex 4 digital I/O pin as an input?
I need to sample high frequency signal in Vertex 4 and wondering about the maximum frequency handling capacity of the digital I/O of the device.
The datasheet does not...
I have also noticed the same during one of my project. I personally feel that there is no need to use two separate processes for implementing a FSM, one for output latching and another for state transition.
I have implemented FSMs for UART and HDLC cores in my project and used a single process...
Do you want to convert a hex value to a std_logic_vector?
There is no standard functions available. You need to write your own conversion function.:idea:
Re: Block Rams
Watch your write control signal. This should be asserted for one clock cycle only.
If this is asserted for multiple clock cycle, then same data will repeatedly go inside the FIFO.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
