Vertex 4 digital I/O usage for high frequency signals

[saikat]

What is the maximum possible frequency of a signal that can be properly handled by Vertex 4 digital I/O pin as an input?

I need to sample high frequency signal in Vertex 4 and wondering about the maximum frequency handling capacity of the digital I/O of the device.
The datasheet does not clearly mention this.

 

[saikat]

OK, I like to ask the question in a different way with an example.



Lets say, there is an external 64 bit bus (LVTTL) whose maximum frequency is 100MHz and it is connected to 64 digital I/O pins of Vertex 4. I need to sample the bus at every 2ns (i.e. @ 500MHz clock), and want to dump the sampled values into an internal FIFO at the same speed of 2ns (i.e. @ 500MHz clock).



Now tell me whether this arrangement will be implementable in Vertex 4? Or can I drive my design @ 500MHz in Vertex 4?