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Recent content by q0w1e2r3

  1. Q

    help to solve Synchronous BOOST DCDC switching PMOS latch-up problem

    How to deal with switching P-channel MOSFET in layout ? For Synchronous BOOST DCDC, when in dead-time, the coil current will be discharged through parasitic P/N junction of large switching PMOS, and SW node (the connection node of NMOS and coil) voltage with be higher than output voltage, so in...
  2. Q

    problem in boost Current mode dcdc

    thanks for your replay. first of all, i will caculate the system loop transfer function when L,C current gain, slope compensation, loading is given, i will get poles/zeros, Q, and gain, then i will simulate error amplifier transfer function, and also get poles/zeros and gain, at last i will get...
  3. Q

    problem in boost Current mode dcdc

    i tape out one PMU chip and when it coming back , i find in one boost dcdc the output ripple is so big , and seems not stable, please see the waveform of test. i wonder if it is system loop stability issue ,and what is the root cause, can you give me some suggestion? BTY, the simulation results...
  4. Q

    How to increase PSRR value in bandgap?

    Re: PSRR in Bandgap use a high dc gain of opamp , PSRR in BG is an important issue
  5. Q

    Need info about designing two stage amplifiers

    Re: two stage amplifier you can use a high gain for fist stage and pash-pull for secong , need compensation
  6. Q

    Questions about the function and characteristics of RHP pole

    poles zeros lhp rhp when you use Laplas transition , you will find waveform will be enlarged . RHZ acts as a left pole
  7. Q

    Suggestions of op amp related circuits and references

    Re: op amp first you can refer to Raziv book or Gray 4th
  8. Q

    what is monte carlo analysis

    it is an analysis which you can analysis posibility of circuit, worst case analysis. when you analysis offset in comparater , it is often used
  9. Q

    Two questions about a ESD circuit

    Re: two questions about ESD resister function is to protect gate of mosfet cuz volatge feedthrough Cgs esd mosfet's drain size is very large to get large current sot that fast discharge
  10. Q

    Hspice err:internal timestep too small in transient analysis

    Re: Hspice error you can select .option for help
  11. Q

    how to get DNL and InL using Verilog-A in Cadence

    I finished a 10bit--20Mhz Pipeline ADC,but i don't know how to measure the DNL and INL .I want to use Verylog-A.Can anyone give me some ideas in details.For example one step,two step.....waht's "vtran=..."mean?Thanks!
  12. Q

    help! an opamp with two stage(Ahjua compensation)

    who can tell me why the simulation result is that as follows? It's closed loop opamp,with the ratio of cap being 2:1.I used two common mode feedback,cuz the opamp is two-stage.I use Ahjua compensation.The schemetic is as follows. The simulation is run several periods to make CM voltage stable...
  13. Q

    What are the reasons of signal distortion in IC and how to minimize it?

    Re: signal distortion mainly non-linearity.solution : feedback,high dc gain ,layout issues,charge injection and many many
  14. Q

    question about the simulation condition?

    ss corner:-100c, -10% voltage supply, high dc gain low speed ff corner:40c ,+10%voltage supply,low voltage supply high speed
  15. Q

    How to make a current source with two transistors?

    Re: current source you can find a book to look at such as Ken martin Added after 10 seconds: you can find a book to look at such as Ken martin
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