q0w1e2r3
Junior Member level 1
How to deal with switching P-channel MOSFET in layout ?
For Synchronous BOOST DCDC, when in dead-time, the coil current will be discharged through parasitic P/N junction of large switching PMOS,
and SW node (the connection node of NMOS and coil) voltage with be higher than output voltage, so in tranditional CMOS process,
P+ /Nwell will conduct and parasitic pnp (p+/n-well/p-sub) will be in active region so that it is subject to latch-up, so how to prevent this risk?
If only in transitional CMOS process, how to achieved?
For Synchronous BOOST DCDC, when in dead-time, the coil current will be discharged through parasitic P/N junction of large switching PMOS,
and SW node (the connection node of NMOS and coil) voltage with be higher than output voltage, so in tranditional CMOS process,
P+ /Nwell will conduct and parasitic pnp (p+/n-well/p-sub) will be in active region so that it is subject to latch-up, so how to prevent this risk?
If only in transitional CMOS process, how to achieved?