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Hi All,
I wanted to add antenna diode to the design of my analog IP which would be integrated to top level.
In pdk they have provided two antenna diodes for positive node and negative node protection:
n+ diff to pwell for positive node
p+ diff to nwell for negative node
Question 1:
How to...
Hello All,
I have a pad ring with corner cell to allow the connectivity of the analog and digital power rails.
Since I am planning to reduce the die area of the chip, I was planning to remove one of the corner cell.
So I am confused if it is recommended to keep all 4 corner cell at each corner...
Hello,
I am learning to create a pad ring for a mixed signal SOC.
Few point I have understood so far are:
1. Have separate Analog and Digital ground and power pins to isolate the noise from both the blocks.
2. Multiple pads for pad supply and ground pin, this is to reduce the equivalent...
As per the theory in most of the papers i found that by scaling sampling capacitor for the lower stages of pipeline we can get power reduction.
But as I am measuring static power consumption in my ADC, I did'nt find any change in power by scaling capacitors.
Please guide me where I am going...
Hello,
I am designing a reconfigurable pipelined ADC with varing sampling rate and resolution.
Can anyone tell me how the opamp specifiation of individual pipeline stage would vary with resolution and sampling rate of ADC?
Cheers
Hello Everyone,
I am designing 12 bit pipelined ADC. I am facing problem to get the accurate gain of 2 from the designed MDAC when I use the capacitors from technology library.
When I replace the CI and CF capacitors with the ideal caps I get accurate 2 gain when I check the residual output of...
Hello everyone,
I did the paracitic extraction of designed layout. But the simulation results of the extracted view gives 40% variation in for phase margin and settling time. I think there is lot of paracitic capacitance adding through my layout.
This is my first layout and now I want to...
I have designed class AB folded cascode OTA (Image attached ref. J Huijsing). I want to achive less than 20 ns settling time.
I found that i acheive better settling near to 60 deg phase margin and above and below it the settling time reduces. So at corner simulation I am not able to achevie...
Thanks!! These are very nice notes for gm/Id method.
But I am stuck at plotting graph for gm/id in Cadence spectre. I am not able to understand how to plot gm during DC sweep. Please guide me with this.
I am designing a Fully diff Folded cascode OTA and for this I need to design a wide swing bias.
I read a lot about gm/Id methodology used to bias transistors in strong inversion for having a good design.
But I could not get get proper rersourse to follow this method. Dose anybody have resources...
This means I have to design a biasing circuit first before proceeding to the amplifier design.
And what about Vncas and Vpcas, should it have bias voltage such that it supplies half current through transistor for class AB operation.
Hi,
I want to implement class AB folded cascode design. I am referring to the circuit from J Baker (attached the screenshot) .
To implement this schematic what bias voltages (Vbias1,2..) should I assume for a known current value flowing through cascode branches.
I have designed an OTA.I have to see Power consumption for different input frequency.
Can anyone suggest me method to simulate this on cadence spectre.
I have designed a two stage opamp. As i needed to check the ICMR, I did DC analysis to see over what voltage range my transistors are in saturation. And then I performed AC analysis by doing parametric sweep of common mode input over that range.
I found 4 dB variation of gain over ICMR range...
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