predator89
Member level 1
Hello,
I am designing a reconfigurable pipelined ADC with varing sampling rate and resolution.
Can anyone tell me how the opamp specifiation of individual pipeline stage would vary with resolution and sampling rate of ADC?
Cheers
I am designing a reconfigurable pipelined ADC with varing sampling rate and resolution.
Can anyone tell me how the opamp specifiation of individual pipeline stage would vary with resolution and sampling rate of ADC?
Cheers