Help with redundancy in conventional SAR ADC

[jatin123]

Suppose i have a 10 bit SAR ADC (conventional switching) with 3 binary weighted redundant bits. C10 C9 C8 C8R C7 C6 C5 C5R C4 C3 C2 C2R C1 with weights 512 256 128 128 64 32 16 16 8 4 2 2 1

How to convert the 13 bit code to 10 bit code.?

I added them like this:

C10 C9 C8
————C8R C7 C6 C5
——————————C5R C4 C3 C2
————————————————-C2R C1

There seems to be a gain error in the output which reduces the range. Is that expected?

 

[dick_freebird]

Those "redundant bits" I imagine would be switched-in replacements for their co-named main bits. Presumably some select logic with RAM, NV or hard trim bits programmed at early test or some cal cycle if rewritable.

 

[D.A.(Tony)Stewart]

This paper describes the operation in detail. The redundancy reduces the C values ADC by 50% and thus chip area and boosts speed 30%.
The 3 redundant bits improve settling time & C ratio error tolerance coarse, fine and final estimation of quantization steps with 1 extra bit per nibble (4b).

https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=c3df525c871f9f8ac21aa94176ccd33e17035ce8