Parasitic capacitance reduction

[predator89]

Hello everyone,

I did the paracitic extraction of designed layout. But the simulation results of the extracted view gives 40% variation in for phase margin and settling time. I think there is lot of paracitic capacitance adding through my layout.

This is my first layout and now I want to debug my layout to reduce paracitics. I wanted to know how I can find the nodes in my layout which is adding more paracitics. Also please suggest me methods to reduce the paracitic capacitance.


Any help will be welcome.
Thanks in advance.

Cheers

 

[SLK001]

What is your circuit? Also, do you have faith in your simulation results?

You should know what makes a capacitor, so where do YOU see the nodes in your circuit?

The only way I know to reduce the parasitic capacitance is to reduce my parasitic capacitors. Shorter traces, removing ground plane from underneath the traces, stuff like that.

 

[dick_freebird]

Using higher metal levels reduces the parasitics to the
substrate "node" (probably not well represented as a
stiff capacitor, but that may be all you get; substrate
resistivity matters).

You ought to be able to select all of the pcapacitor
instances that are placed in the analog_extracted
(or whatever, similar; the one that is produced and
perhaps "refined" for analog / RF backannotation
has a whole mess of minuscule instances placed
with named-net connections). You might be able
to pull a layout tree on that _extracted view and
see a huge number of them in the report. Export
and sort & sift for capacitance, or dig for the nets
that you think matter. You can highlight the net
and see pcapacitor terminals light up (if you are
zoomed in sufficiently) and follow the bouncing
ball to the other side of it, to see "C to what?".

In RF processes you may also be given adjunct
pcapacitors from the transistors themselves, to
properly model the close-in interconnect driven
capacitances (esp. look at Cdg). You might be
able to gain some significant reduction there by
backing the drain metal off from the gate, you
may have to flatten and make-cell to do this but
even a couple of tenths of a micron can help a
lot, while costing not-much Rd increment in a
silicided S/D process (which almost all are).

Also be sure you check whether your PDK has
both pre-layout (where an estimate of wiring
close-in C is embedded) and post-layout (where
only the bare-device C is modeled, expecting the
parasitics to be lumped elsewhere) models set; if
so, be sure you don't use pre-layout models with
a post-layout netlist or you'll be doubly penalized.

 

[Ata_sa16]

Some hints about layout:

1) If you have differential circuit you have to make it super symmetric. and after layout you have to find input offset and simulate the circuit after applying that offset.

2) If you have high current increase metal width,

3) use multiple vias not only one !

4) Avoid routing with poly layer.

5) Keep transistors close to each other as much as u can to reduce your routing path.

6) if u have 2 transistors which sources or drains are connected to each other. u can share their drain or source area in order to decrease cap.