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Recent content by orangelogic

  1. O

    how to calculate the setup and hold time ,thanks

    hold time and setup time in digital circuits(ppt) Hey, thanks a very good ppt....
  2. O

    Asynchronous FIFO Depth with Rd clk Duty Cycle 25%

    If read clock is faster than write clock, what role does FIFO play here, it gets me confused.....
  3. O

    Latch from a flip flop

    hey this is a weird question, why would someone require to make a latch from a flip-flop. but I heard that this question keeps popping in interviews....
  4. O

    Interfacing VHDL design with a Verilog testbench

    Hello, I am working on asic project and I have a IP core in VHDL. Now, i need to write the verilog code for the testbench. can someone tell me how do I do this interfacing. I understand that there has to be some wrapper around my VHDL design. But can someone throw more light on this. Thanks in...
  5. O

    floating point question

    I am trying to design a FFT block in verilog and I am stuck with the floating-point adder unit. Can anybody help me the rounding logic which involves the usage of sticky bit.
  6. O

    How to calculate the depth of FIFO and what are the designs contraints for it?

    fifo calaculation interview this was very helpful
  7. O

    Beginner - Layout techniques

    thanks a lot, this is an extensive resource for layout begineers
  8. O

    Recognizing of a bit-stream that is divisible by 5

    can someone explain this problem by a state diagram...
  9. O

    Exercise problems in FSM

    thanks, many good examples on FSM
  10. O

    How to calculate the depth of FIFO and what are the designs contraints for it?

    fifo diagram hey microe_victor, can u expand a little more on the FIFO depth calculation.... thanks
  11. O

    Selecting architecture for an adder in Cadence

    I am about a make a adder architecutre in cadence using static cmos, can someone suggest a useful resource which can help me in selecting a specific architecture among "carry lookahead" "carry skip" "carry select" and few others.
  12. O

    Question regarding the faults in a CMOS gate

    Re: A CMOS question I am not using this conficuration for any purpose, I am trying to charcterize the circuit for different faults. Answer given by shaikhsarfraz is correct , I think, that when both the inputs are 1, vdd and ground is short and output is zero. and when the transistor...
  13. O

    Question regarding the faults in a CMOS gate

    I have a question regarding the faults in a CMOS gate: " What If in a 2 input nand CMOS I short the drain and source of one pmos transistor, what would be the behaviour of the nand gate?
  14. O

    Looking for good free HDL simulator

    Re: hdl simulator thanks for the link, and can u suggest any simulator for verilog,, there are many out there, but which one would be better for a beginner
  15. O

    Looking for good free HDL simulator

    hdl simulator I am learning hdl languages, can anybody suggest a good and a free simulator to start with. Thanks in advance
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