how to calculate the setup and hold time ,thanks

[ydragon]

setup time and hold time based questions

I think the anwser is C and C:
for 1, the extra delay is 2ns, clk delay is 1ns, total added delay is 1ns
setup is 1+2=3ns, Hold is 2ns-1ns=1ns;
for 2, the max frequency is 1/(2+2+4)=125MHz;

 

[nepuba]

calculate setup time total time

basic principle is very important

 

[linkfox]

how to compute setup and hold time

hi
if the delay is 4ns
i think setup time is 5ns and hold 0ns
frequency is also 125mhz

is it r?

he asked if the NOT gate is 4ns, not the OR gate, so I think tsu is 0 and thold is 4ns.

 

[Davood Amerion]

calculate 43 times 27

I realized that my previus answer was incorrect.
So I correct it as below.
1. (C)
2. (C) just if this single FF is used (no other combinational circuit is used).

 

[cshekhar]

setup time and hold time +ppt

for given ckt freq will be
2(Setup) + 2 (Xor Delay) - 1(Buffer delay)= 1/3ns

Added after 17 minutes:

Please mail me SeqCktTiming.ppt on cshekhar_vlsi (at) rediffmail.com. I dont have enough points for downloading it.

Thanks in advance.
cshekhar

 

[tooh83]

digital setup hold time calculation

I think

1) C
2) D

 

[ljxpjpjljx]

calculating setup time and hold time

also plot the whole picture and we should check the 4 corner?

 

[zeevg]

creating time delays setup hold c

more questions

 

[echo47]

how to calculate setup time and hold time

To all you newbies begging for the PPT file, try clicking the link that says "Free Mirror (no points)".

 

[gaobin0628]

calculate setup hold time

answer
c
c

 

[niddsy]

setup & hold time(ppt)

(setup time at pin of whole chip) =
(setup time of flip-flop data pin)
- (min clock delay from chip pin to FF pin)
+ (max data delay from chip pin to FF pin)

Added after 49 seconds:

(hold time at pin of whole chip) =
(hold time of flip-flop data pin)
+ (max clock delay from chip pin to FF pin)
- (min data delay from chip pin to FF pin)

 

[orangelogic]

hold time and setup time in digital circuits(ppt)

Hi,

I have a good ppt for setup and timing analysis. Pls refer it which will help u lot

Hey, thanks a very good ppt....

 

[ASIC_intl]

setup and hold time maximum

HI satyakumar

Do u have any document that have definition of setup and holdtime?

 

[jjftt]

calculate setup and hold time

the answer is
c
c

 

[alanzheng]

The answer is :

1. c

2. c (the buffer for clock will not affect the maximum frequency)

Please think it over if you select others, because the wrong answer maybe mislead the junior guys.

 

[gkulathu]

I think max frequency is 250MHz.
Tclk->Q need not be taken for calculating max freq, just setup time is enough. fmax=1/(Tdxor+Tstup)

 

[smilewithshiv]

Assuming XOR delay as propogation delay (Tp).

Effective setup time: Tsu + Tp - Tsk = 2 + 2 - 1 = 3
Hold time: Th - Tp + Tsk = 2 - 2 + 1 = 1

Circuit operating frequency:
Tco + Tp + Tsu - Tsk = 4 + 2 +2 - 1 = 7

Closest answer in given options is 125 MHz.

Circuit should meet hold time requirement. If any hold time violations, circuit need to be updated with enough buffers to resolve hold time violations, operating frequency change doesn't ensures meeting of hold time requirements.

 

[ysk2020]

setup time = (clock period)Tc – (datapath delay)Tdp – (clk-Q delay)Tff-(clock path delay)Tdc
Tsu



comment on my inference???

 

[Pawan_tej]

Hi,
Please mail me the ppt @pawantej28@gmail.com. I am unable to download.

Rgds,
pawan