Asynchronous FIFO Depth with Rd clk Duty Cycle 25%

[asicganesh]

I want to calculate the Asynchronous FIFO depth that will meet both overflow and underflow cases.. here are my constraints:

1. Write Clock is 25MHz and Read Clock is 100 MHz
2. Duty Cycle of Read clock is 25%

Let me know if there are any articles or papers having all such scenarios to calculate AFIFO depth

Thanks

 

[feel_on_on]

u need to tell us how much bytes sequence data you need to send .

 

[asicganesh]

The Write and Read Byte sequence are 2 bytes

 

[kushagrak]

I am very much eager to know how to cal the depth....

 

[orangelogic]

If read clock is faster than write clock, what role does FIFO play here, it gets me confused.....

 

[feel_on_on]

I think you should set EMPTY flag until fifo depth data have been written to fifo,then...cancel EMPTY flag and begin to read .