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Re: Synthesizable vhdl
For a synthesizable design, ensure that all the logic is based on a clock signal (i.e. synchronous). You cannot implement 'wait statements' or the like as synthesis does not evaluate time, only event driven states.
good luck.
You have state 1 (S1) feeding back to S1 - should have next state assigned to S2. Tools will not implement an state machine without being able to resolve all the states.
Re: LFSR design question
Xilnx has a application note regarding LFSRs (XAPP210). The last section has all the taps for a 3 to 168 clock cycle LFSR. See hxxp://www.xilinx.com/bvdocs/appnotes/xapp210.pdf
Re: IPC Standards
If you are desiging to IPC standards, go to h**p://www.pcblibraries.com/ and download their IPC-7351 viewer. The authors of this website are part of the IPC committee and have some very valuable tools for automatically creating IPC complient footprints for Allegro, Pads...
Conventional binary counters use complex or wide fan-in
logic to generate high end carry signals. A much simpler
structure sacrifices the binary count sequence, but
achieves very high speed with very simple logic, easily
packing two bits into every CLB. Such Linear Feedback
Shift-Register (LFSR)...
What version of Modesim are you using? The default resolution Modelsim uses is 1 picosecond, so any simulation of a minute requires an enormous amount of clock cycles. This resolution can be changed. Also, this will syntesize using a 25 bit counter, which can be hard to route with a 25MHz...
What language are you using? In VHDL I would create a 3 state FSM using a typical FSM format. The first state would be to identify the "01" pattern. The second state would initiate a counter which would count the number of bits to skip. The third state would be to compare/capture the...
I agree with the others, try a PIC16Cx for starters - www.microchip.com has a number of good application notes - and if you have access to a distributer, are pretty good about getting you started with a demo board.
If you don't want to purchase a book, try going to the Aldec site and using their tutorials. It will get you started and they have a great Verilog primer with over 130 examples.
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