Tips for writing synthesizable VHDL for RTL

[aramosfet]

I've heard only synthesizable on rtl descriptions can be realized on hardware.
So how do we write rtl descriptions? What are the do's and dont's while writing a vhdl code for synthesis?

 

[Tan]

Re: Synthesizable vhdl

Hi,
Yes,only synthesied code can produce RTL.
Do's : writing the code in correct syntex.
Dont'sont think in software point of view while writing for hardware design.

Try to draw the design on paper first and anlyse it and see what hardware is produced by you on the paper
And try to design it on xilix or whatever tool you use,syntheise and verify whether you got the same design or not.

I hope this will help you

cheers.

 

[MWind]

Re: Synthesizable vhdl

For a synthesizable design, ensure that all the logic is based on a clock signal (i.e. synchronous). You cannot implement 'wait statements' or the like as synthesis does not evaluate time, only event driven states.

good luck.

 

[aramosfet]

Re: Synthesizable vhdl

Is it acceptable to use variables in a design for synthesis?
What is the difference between signal and variable interms of synthesis?
are variables and signals implemented in the same way on the fpga?

 

[yasser_shoukry]

Synthesizable vhdl

You must take care of some criterions while writing your RTL code.

What I mean is that each "VHDL Process" will be infered in either "Combinational" , "Synchronous Sequential" or "Asynchronous Latch". You must take care which one of these you want your code to be infered to.

Here are some rules:
-For Combinational Circuits:
1)All signals in the senstivity list must be "Level sensetive", no edges at all
2)All cases must be covered
3)Do not write a signal in the senstivity list before you read it.

-For Synchronous Sequential Circuits:
1)All Registers must be synchronized with the same clock.
2)All signals in the senstivity lsit must be edges (clock edge and reset edge)
3)Do not forget the reset value.

If your RTL code does not match either "Combinatiolnal" rulse or "Synchronous Sequential" Rulse, either it will not be synthesizable or an "Asynchronous Latch" will be infered. Please read the synthesis repoert carefully as "Infered Latches" cab ruin your design.

Good Luck

 

[Tan]

Re: Synthesizable vhdl

Yes,you can use variable.
variable assigns value immediately without any delay.
signals produce flip-flops and variables produce wires during synthesis..
I hope this is clear
all the best