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Recent content by lunren

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    CDM ESD event protection

    Hello, I have a question about CDM ESD protection. If the cross domain is between core devices and IO devices, the core devices are TX and IO devices are RX. Since the RX is thick devices, in this case, how necessary is it to implement cross domain CDM protection (assume CDM spec is 500V) for...
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    Loop bandwidth and effect of power supply noise on PLL?

    power supply filter bandwidth From page 573 of Design of CMOS radio-frequency Integrated Circuits by Thomas Lee, it is said that we should increase bandwidth if power noise or other noise generated inside the PLL. However, if reference phase noise is considered, we should decrease the...
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    Loop bandwidth and effect of power supply noise on PLL?

    loop bandwidth Considering power supply noise, if we want to decrease its effect on PLL, should we increase loop bandwidth or decrease bandwidth? If the VCO is composed of transconductor (PMOS)+ICO+power match, I think the power supply noise has the some effect as the noise of loop filter on...
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    Receiver VS Spectrum Analyzer:about 3rd intermodulation test

    Re: Receiver VS Spectrum Analyzer:about 3rd intermodulation If 10dB attenuator was added, then all frequency (including intermodulations) passing the 10dB attenuator will be attenuated by 10dB. In this case, the displayed spectrum must change with or without the 10dB pad, right? If not, where...
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    Receiver VS Spectrum Analyzer:about 3rd intermodulation test

    Re: Receiver VS Spectrum Analyzer:about 3rd intermodulation Thank you very much for your reply. But what is the 10 dB pad? Can you (or anyone) explain its function? Sorry that I don't know it.
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    Receiver VS Spectrum Analyzer:about 3rd intermodulation test

    Hi all, Assuming that we are going to do two-tone test for 3rd intermodulation. The simplified test diagram is: a signal generator followed by Receiver and Receiver followed by spectrum analyzer. We will see 3rd intermodulation from spectrum analyzer, but how do you know the 3rd...
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    Help, simulation of PLL's phase noise

    phase noise in pll, calculation I know different noise source has different TF. What I said is only a example. I mean if I want to use matlab to calculate phase noise, how should I get the vector of the TF? By matlab itself or by simulator such as spectre?
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    Help, simulation of PLL's phase noise

    cppsim different frequency phase noise To Mazz, Thank you very much for your reply. So the conclusion is that mathematical method is a better way to do phase noise simulation. If the noise or phase noise of sub-blockes of PLL is called data, the transfer function is called TF, then the...
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    Help, simulation of PLL's phase noise

    simulation of phase noise in matlab Yes, I know Designer's guide. But a friend in Broadcom said that using VerilogA/MS is not good to simulate phase noise of PLL. He said the best way is to use matlab. So I want to know the procedure to use spectre and matlab to simulate PLL phase noise. Any...
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    Help, simulation of PLL's phase noise

    pll mathematical equation Thanks a lot. I know how to simulate VCO's phase noise, but I need some guide to show how to simulate the phase noise of the whole PLL.
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    Help, simulation of PLL's phase noise

    pll phase noise Hi all, I want to simulate the phase noise of the whole PLL. It is easy to simulate the phase noise of the individual blocks in the PLL, but how to simulate the phase noise of the whole PLL? Should we use Mablab or Cadence to build the noise model for the PLL? Any suggestion...
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    Help: Cadence error: V5: Waveform type must be specified

    waveform type must be I use Cadence to work on a project, but there is a error: V5: Waveform type must be specified if any waveform parameters are given. I searched internet, it seems that lot of people meeting this problem, but no good solutions. Anybody here can give some ideas? Another...
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    Need resources about PLL testing

    Hello, everyone, Our chip which includes a 500MHz pll was fabricated with smic 0.18um technology. It works well. Now, we are going to evaluate the 500MHz pll. Can you give some hints or papers or links about the PLL test? We are lack of such experience. Thanks in advance. Best regards, Lunren
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    Looking for references about Spread Spectrum PLL

    Re: Spread Spectrum PLL Here is what you want. Hope it helps.
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    What's the exact meaning of beat frequency in PSS simulation?

    Re: About pss and jitter From the paper, The auther just use the phase noise of one "frequency point" to calculate the jitter, but not use the integral of a "frequency range" to calculate the jitter which is the method presented in the maxim's paper. Why? Thanks.

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