Loop bandwidth and effect of power supply noise on PLL?

[lunren]

loop bandwidth

Considering power supply noise, if we want to decrease its effect on PLL, should we increase loop bandwidth or decrease bandwidth?

If the VCO is composed of transconductor (PMOS)+ICO+power match, I think the power supply noise has the some effect as the noise of loop filter on control voltage, which is a bandpass filter and the bandwidth is just the PLL loop bandwidth (=2*ζ*ωn). So if this is the case, we should decrease the bandwidth in terms of the power supply noise (at least for this specific VCO topology).

Any comments?

Lunren

 

[lunren]

power supply filter bandwidth

From page 573 of Design of CMOS radio-frequency Integrated Circuits by Thomas Lee, it is said that we should increase bandwidth if power noise or other noise generated inside the PLL. However, if reference phase noise is considered, we should decrease the bandwidth. Therefore, there is a optimized bandwidth so that the output phase noise of PLL is minimized.

Thanks.

 

[intirajesh]

pll loop bandwidth effects

the supply noise transfer function (from vco to output phase) is bandpass is nature with the transfer function.

Supply-noise mitigation techniques in phase-locked loops
Arakali, A. Talebbeydokthi, N. Gondi, S. Kumar Hanumolu, P.
Sch. of EECS, Oregon State Univ., Corvallis, OR;
This paper appears in: Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European

 

[biff44]

power supply bandwidth

If properly designed, op amps can have power supply noise rejection. In that case, you want to broaden the bandwidth of the PLL up to the point that you start to lose--ie where the multiplied up phase noise of the reference frequency starts to dominate.

If there is poor power supply noise rejection in the op amps, then you want to lowpass filter right at the VCO tuning port.

Of course, there are other system level factors to consider. For instance, a lot of communications systems can ignore close-to-the carrier phase noise (due to the carrier tracking loop), so worrying about low frequency power supply noise is not as important.

 

[sainiparvesh]

Hi,
If the bandwidth of PLL is e.g. 1MHz then what kind of noise should be applied in its spice simulations to measure the supply noise impact on PLL phase noise performance?

 

[sainiparvesh]

Hi,
If the bandwidth of PLL is e.g. 1MHz then what kind of noise should be applied in its spice simulations to measure the supply noise impact on PLL phase noise performance?

What about substrate/ground noise? Are we assuming that proper substrate/ground guardring with DeepNwell(Isolated PWELL) will take care of it?