What's the exact meaning of beat frequency in PSS simulation?

[lunren]

Dear all,

1) In pss simulation, What's the exact meaning of beat frequency. If the circuitry is a VCO, I should set the beat freqency equal to the VCO oscillation freqency. But if the circuitry is not a VCO, how to set the value of beat frequency?
2) In pss simulation of VCO, the beat frequency does not need a very precise value?
3) How to convert the phase noise to jitter in cadence ADE?

 

[advaita]

eda cadence jitter sim

Hi

1) If the ckt. is not a VCO (or oscillator) and is having a periodic behaviour, then the driving signal must be periodic. Set the beat frequency to its fundamental.
Moreover, if you want to measure steady state stable output (say the final settled value of an opamp to a step response), I think you can give any beat frequency. If you're having convergence probelms then try putting a dummy clock source in your setup.

2) Not very preicse is needed. But do give initial conditions for simulation otherwise you'll have convergence issues. Best option is to first do a transient and then do the pss.

3) See an app. note from Maxim regarding phase noise to period jitter conversion: **broken link removed**
Implement it using the calculator.

 

[lunren]

pss beat frequency

Hi, thanks for your reply

If the circuitry have a periodic input frequency, but a vco or oscillator is also included into the circuitry, how to set the beat frequency.

Best regards,

Lunren

 

[advaita]

pss beat frequency spectre

The aim is to set the beat time period such that you have integer number of cycles of all the sources in that period.

e.g. if you have 2MHz and 5MHz in your setup, you can set beat freq. = 1MHz
if you have 2.5MHz and 5MHz in your setup, you can set beat freq. =2.5MHz

It wil be better to choose the driving frequency wisely (for simulations) so that you get a decent (read - not too small) value of beat frequqncy.

Also, there are analysis like qpss which come in handy when the beat frequqncy you need in PSS comes out very small.
See **broken link removed**

 

[lunren]

Re: About pss and jitter

Thanks, advaita.

As I understand so far, we must set a beat frequency value just for convergence in pss simulation, am I right?

 

[advaita]

Re: About pss and jitter

We must set a beat frequency value just for convergence in pss simulation, am I right?

Basically yes.

BTW, are you facing any problem in any particular setup? If so, maybe it can be discussed. Otherwise, if we start digging into how the pss algo. works, it'll be a big mess

 

[lunren]

Re: About pss and jitter

Hi, advaita,
Because this is the first time for me to use PSS to simulate circuits. Except how to setup a pss simulation, I also wondering some questions for example how the PSS works, yes it is really big question.
BTW, do you had read Ken's paper "Predicting the phase noise and jitter of PLL-based frequency synthesizers?

 

[advaita]

Re: About pss and jitter

Hi

The paper is present at
https://www.designers-guide.org/Analysis/PLLnoise+jitter.pdf

Did you have anything to discuss in the paper?

 

[lunren]

Re: About pss and jitter

Hi

The paper is present at
h**p://www.designers-guide.org/Analysis/PLLnoise+jitter.pdf

Did you have anything to discuss in the paper?

From the paper, The auther just use the phase noise of one "frequency point" to calculate the jitter, but not use the integral of a "frequency range" to calculate the jitter which is the method presented in the maxim's paper. Why? Thanks.