Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
aulvs
Hi guys,
I am currently using Assura320 with EXT712. I have few modules that passed DRC and LVS. I ran RCX from the Assura (which is set to call EXT) and successfully extracted the parasitic components. However as I was running simulations I realized that the netlist generated from the...
from to derived clocks
Thanks heaps!
I really needed some kind of confirmation, I guess I will create a virtual clock and reference the output FFs to that.
THanks again!
Regards,
virtual clock design compiler
Thanks heaps,
I will give this a try,
:D
Added after 1 hours 48 minutes:
Hi,
create_generated_clock works beautifully.....
However, when I try to constrain external_delay on some of the pins that are driven by this generated_clock, I receive an error...
derived clock
Hi All,
Could anyone tell me what is the standard way of generating a derived clock?
For example I have a design that has one clk input (4MHz), and then in some of the submodules, I have a 2 Mhz clk derived from the main clock and then within these submodules i have 1 MHz clock...
Hi All,
When designing a digital block with asynchronous reset, should this reset be buffered?
Some of the standard templates (for sdc) seems to have the reset port as an ideal_driver and path disabled. If this is the case, wouldn't the reset pin be overloaded?
Currently I have set the...
Hi All,
I have a simple layout which consists of some of the digital logic cells provided by the manufacturers.
When I try to run a DRC check, I get the following error messages.
*WARNING* Inconsistent DBUPerUU in the design
*WARNING* 160 is not the same as 1000
Failed to build VDB
*WARNING*...
gate simulation disable timing
Hi,
I should have posted an answer to the question that I have posted once I have found an answer to it, however I forgot to do so. Yeap the problem was due to one of the signals not being reset... (quite embarassing) Once this was fixed all the x's went away...
Hi,
I followed what you have recommended me in the previous reply, which was using ncverilog command.
I can straight away use the ncverilog within the nclaunch command prompt to import the verilog netlist along with the tech libs and UDPs into the worklib and used ncshell to generate the...
Thank you very much for the reply,
I was actually wondering whether this can be used with a vhdl test bench.
ncverilog seems to take in verilog testbench (or top design unit) since ncverilog just calls all three functions, ncvlog, ncelab, ncsim at one go. Please correct me if i am wrong.
I...
uselib ncelab
Hi All,
Could someone conirm me how to include the tech library files and the required UDP to a synthesized verilog netlist, so that I can run simulations using the ncsim? I am just wanting to verify the functionality of the netlist, so no SDF the elaboration done with timing...
using clock in gate level codes
Hi All,
I am quite new to the digital synthesis and came across a problem which I cannot really seem to be able to debug...(to be honest, can't narrow down the problem).
I wrote relatively small vhdl code, mainly consisting of FSMs. I ran simulations using...
Hi everyone,
just wondering whether anyone tried installing incisive_ius58 via installscape. for everytime I am trying to install from a download-archive, but I am coming across
"Could not unpack" errors.
Could someone help me out with this?
Thanks
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
