post synthesis simulation

[lhsj81]

uselib ncelab

Hi All,

Could someone conirm me how to include the tech library files and the required UDP to a synthesized verilog netlist, so that I can run simulations using the ncsim? I am just wanting to verify the functionality of the netlist, so no SDF the elaboration done with timing check disabled.

So far I included the libraries using the `include directive (in the netlist.v), is this correct? Or am I supposed to be using `uselib?

When I include `uselib directive, the compiler throws an error saying that the library that I have provided can not be translated into lib=<lib> (I am using nclaunch/ncvlog/ncvhdl and RTL_compiler).

Thanks,

 

[no_mad]

hi,

You need this option:
-y <directory> +libext+.v --> Specify a lib directory to be used
-v <filename> --> Specify a lib file to be used

On your x-term, type > ncverilog -help.
You'll see all the support dash options.

Hope it helps.

 

[lhsj81]

Thank you very much for the reply,

I was actually wondering whether this can be used with a vhdl test bench.

ncverilog seems to take in verilog testbench (or top design unit) since ncverilog just calls all three functions, ncvlog, ncelab, ncsim at one go. Please correct me if i am wrong.

I was wondering if I am to do this in nclaunch, in multi step mode. When and where should I include the tech lib and udp files?

Thanks again!

 

[no_mad]

hi lhsj81,

Honestly, I'm not familiar with nclaunch + multi step mode. Thus, sorry I cant help you much.

Perhaps, someone else can share their experience with us. Thanks.

 

[lhsj81]

Hi,

I followed what you have recommended me in the previous reply, which was using ncverilog command.

I can straight away use the ncverilog within the nclaunch command prompt to import the verilog netlist along with the tech libs and UDPs into the worklib and used ncshell to generate the component declaration of the verilog file in vhdl.

I then checked the cds.lib, and I can see that the appropriate tech libs have been imported properly. I then compiled the vhdl testbenches, without any errors, But now I came across another problem (which i did post yesterday differently)....

When I now elaborate the design, with the timing checks disabled, and when I run the simulation, the following signals are obtained:
1) when reset is low, all the outputs are initialized properly
2) when reset is high, after 3 cycles of the input clock, all the outputs become 'x' (don't care) state

To be honest, if all the outputs are 'x'... not even sure where I should start debugging...Would anyone by any chance know what I might be doing wrong?

Thanks,