[SOLVED] Using SRAM Macro for simulation and synthesis

[abhishektyagi]

Hi everyone,
I got my hands on this ARM Artisan memory compiler for generating SRAMs. I generated .v, and .lib files from it to carry out RTL simulations and synthesis.But I have been finding it difficult to even do basic read and write operations on it. I was wondering if I could seek your help regarding the same.

For ex: If I want to write to the memory, as per the documentation, SRAM requires me to have chip_enable as LOW and write_enable as active LOW as well. But when I look at the verilog file, there is no corresponding block that will write the memory location upon this condition being fulfilled.

Instead, the .v file does have some tasks like loadmem, dumpmem etc. I am wondering if that is the way to go if I want to read and write to/from memory.

It's my first time using SRAM Compiler, so I am not sure if SRAM Compilers are supposed to spit out .v files in such format

 

[cike128]

Generally, there is an option to generate Verilog behavioral models in the memory compiler. You need to use this .v file during simulation, but you do not need to worry about the internal logic of the model. You can simply use the SRAM controller to read or write. For synthesis, you need to use the library database file, which is usually automatically generated when generating the SRAM.

 

[ThisIsNotSam]

the generated verilog file is a model, it does not describe the details of the physical implementation.

the loadmem stuff is there as a workaround so you can put your memory in a given state without having to write address by address over 10000000 clock cycles. in the physical memory, this functionality does not exist.

 

[abhishektyagi]

Thank you for the responses. I figured out the issue here: I was trying to read/write really early. I just waited for a couple of cycles before enabling the write to the chip