lhsj81
Newbie level 6
using clock in gate level codes
Hi All,
I am quite new to the digital synthesis and came across a problem which I cannot really seem to be able to debug...(to be honest, can't narrow down the problem).
I wrote relatively small vhdl code, mainly consisting of FSMs. I ran simulations using series of input vectors and confirmed that the output is correct. I then used RTL_compiler to synthesize the code.
I created an ideal input clock (read from somewhere that for the input clock, I can set it to be ideal, for I will be using clock tree synthesis during P&R process), external_delay (both input and output) and various other constraints that were present in the detailed RTL_compiler synthesis template provided in the RTL_compiler document.
The synthesis ran without any errors and now I wanted to carry out functional verification using the ncsim, without any SDF file, just to confirm that the Gate level netlist was correct. I used a vhdl testbench with the verilog gate-level netlist using multi-step mode in nclaunch (for compilation of verilog, I included the required technology libraries), which compiled without any errors. I elaborated the code and made sure that for the verilog compilation options, I set zero delay, and disable timing checks (also followed similar procedures for the vhdl compiler equivalent).
Now when I run simulations using same set of bit-vectors that i used in RTL simulations, using ncsim, I get 'x' (don't care state) for all the outputs. At time 0, when the reset is low, the outputs held correct values, and after few clock cycles after the reset turned to '1', all the outputs became 'x'. Even if the gate-level netlist is wrong in terms of timing for setup or hold times, I thought I should still get valid outputs for I set the mode to zero delay mode, is this correct? If this is wrong, i guess that I should re-synthesize with better constraints.
Any directions for debugging would be greatly appreciated.
Thanks in advance.
Hi All,
I am quite new to the digital synthesis and came across a problem which I cannot really seem to be able to debug...(to be honest, can't narrow down the problem).
I wrote relatively small vhdl code, mainly consisting of FSMs. I ran simulations using series of input vectors and confirmed that the output is correct. I then used RTL_compiler to synthesize the code.
I created an ideal input clock (read from somewhere that for the input clock, I can set it to be ideal, for I will be using clock tree synthesis during P&R process), external_delay (both input and output) and various other constraints that were present in the detailed RTL_compiler synthesis template provided in the RTL_compiler document.
The synthesis ran without any errors and now I wanted to carry out functional verification using the ncsim, without any SDF file, just to confirm that the Gate level netlist was correct. I used a vhdl testbench with the verilog gate-level netlist using multi-step mode in nclaunch (for compilation of verilog, I included the required technology libraries), which compiled without any errors. I elaborated the code and made sure that for the verilog compilation options, I set zero delay, and disable timing checks (also followed similar procedures for the vhdl compiler equivalent).
Now when I run simulations using same set of bit-vectors that i used in RTL simulations, using ncsim, I get 'x' (don't care state) for all the outputs. At time 0, when the reset is low, the outputs held correct values, and after few clock cycles after the reset turned to '1', all the outputs became 'x'. Even if the gate-level netlist is wrong in terms of timing for setup or hold times, I thought I should still get valid outputs for I set the mode to zero delay mode, is this correct? If this is wrong, i guess that I should re-synthesize with better constraints.
Any directions for debugging would be greatly appreciated.
Thanks in advance.
