Derived clock constraints

[lhsj81]

derived clock

Hi All,

Could anyone tell me what is the standard way of generating a derived clock?

For example I have a design that has one clk input (4MHz), and then in some of the submodules, I have a 2 Mhz clk derived from the main clock and then within these submodules i have 1 MHz clock.

If such is the case, is it preferred to have 3 separate main clock ports on the top design?

I was trying to set some constraints in DC compiler, however, I cannot set any derived clock as an ideal driver. If I would like to use the CTS during P&R, is having 3 separate main clock ports on the top design the only way ? If I would like to P&R the whole design rather than partitioning them?

Thanks,
Regards,
Louis

 

[ljxpjpjljx]

generated_clock constraint

also you should consider the P & R information!

 

[MarcS]

derived clocks

Hi lhsj81:

No, you do not define 3 top-level clocks.

You typically create a derived clock by feeding the clock signal into a divider (= a chain of FFs). This generates a divide-by-2 and divide-4 , etc. clock signals.

You only need one top level clock input on your design for this. In the SDC you use the "create_clock" to define this top-level clock.

For the derived clocks you use a "create_generated_clock" statement in the SDC (see **broken link removed**).
This explicitly establishes the relationship between the parent clock and each generated clock.

The P&R systems all know how to deal with generated clocks, and you can implement the design flat.

Hope this helps.

 

[lhsj81]

virtual clock design compiler

Thanks heaps,

I will give this a try,



Added after 1 hours 48 minutes:

Hi,

create_generated_clock works beautifully.....

However, when I try to constrain external_delay on some of the pins that are driven by this generated_clock, I receive an error saying that
-clock object_deleted (by the way I am using RTL_compiler).

Am I doing something wrong here? Or can't I set external-delays with the generated clocks for it is expanded to real clocks during timing of the design?

If so, what would be the best way to set external-delays on some of the pins that are driven by the generated clock?

Thanks in advance,
Regards,

 

[MarcS]

generated_clock

Hi lhsj81:

I am not that familiar with RTL Compiler but I think an input/output delay must reference a top-level clock (or a virtual clock).

You see, an external delay is required because STA timing is always FF-to-FF. In the case of a path connecting to an IO port, the launching FF is missing for an input port and the capturing FF is missing in the case of an output port. Essentially, the design only contains part of the FF-to-FF datapath and the rest is off-chip.

Let's look at an output port (it's similar for an input port): The signal is launched from a FF in your design, and the STA tool imagines there is a capturing FF somewhere off the chip. The STA knows about the part of the datapath delay that goes from the launching FF to the output port. But it needs the external delay constraint to know how long the datapath delay is from the ouptput port to this imaginary capturing FF off-chip.

Which begs the question: What clock signal is driving this 'imaginary' FF that is capturing the signal off-chip? By default it is the same clock signal that is driving the launching FF (or you can define a virtual clock to drive the imaginary capturing FF).

I think that the off-chip capturing FF cannot see an internally generated clock signal. So I think (and I am not 100% sure of this) that you must reference the external delay to a top level clock.

 

[lhsj81]

from to derived clocks

Thanks heaps!

I really needed some kind of confirmation, I guess I will create a virtual clock and reference the output FFs to that.

THanks again!
Regards,