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First: You can not have procedural assigns (i.e. assign statements) inside the initial block.
Second: initial blocks are ignored for synthesis except a few very specific case in some synthesis tools, your whole code seems inside the initial block.
Coding style needs to be corrected.
Thanks...
Harinisas,
First of all you have not mentioned the FPGA/Device/Family that you are using, so please specify. Every FPGA has set of user guides that you can read and use to know how to configure their FPGAs. Go through following link if you are using spartan-6 from Xilinx...
Can you try following:
#################
integer i;
reg [63:0] MyVar;
reg [3:0] EndVar
begin
for (i=0; i<10 ; i =i+1) begin
EndVar= MyVar[i*4+3- :4];
...
...
...
end //for
#################
Let me know if it works.
Thanks,
Fpgadsgnr
fouwad,
Attaching the testbench for you, try this and check both post pnr and behavioral simulation matching. Further I leave it to you to analyze and find why this one is working.
`timescale 1ns / 1ps
module testbench;
// Inputs
reg clk;
reg [0:31] Iid2alu;
reg [0:31] rs1_data;
reg...
In that case, you manually need to look into the path with max number of levels and estimate using the timing equation (with Tcomb, Tsetup, TclktoQ etc). But that can an estimate only and if the design is complex, it will be difficult and even more time consuming.
Fpgadsgnr
You need to know more about propagation delays and 'static timing analysis', look for logic levels into the path of your design after synthesis as well as PnR, you will get the answer of your question. LUTs, FFs, IOs inside FPGA have certain propagation delays, and larger the number of logic...
Hi TonyM,
Your description looks mature, and I agree with that. To further help Prashanth.vinnakota, I am attaching the classical CMOS implementations for Latch & Flip Flop.
If you are interested to go in further details then I would recommend reading following book:
CMOS: Circuit Design...
Do you work on FPGAs? Haven't you noticed the impact of unwanted latches in your design? Now atleast when you are answering to someone's query, you should not be casual and make such statements.
My emphasis was to contradict following of your statement
Originally Posted by...
Hi,
What kind of delay parameters you want to know before synthesis? Maximum freq of the design is calculated based on the critical path of the design, and to calculate that you need to know propagation delays of LUTs, setup & hold times of flipflops of actually used. And this information can...
Which FPGA/Device/family you are targeting? FPGAs won't give performances beyond 500MHz (needs extra efforts to really make your design work at this freq).
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