RTL view removed many blocks and added buffers instead

[mohamedtarek]

i would be really grateful if someone could tell me what is wrong with this code


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY LPM;
USE LPM.LPM_COMPONENTS.ALL;
LIBRARY work;
USE work.ALL;

ENTITY similarity_indicator IS
PORT
(
alpha_1,beta_1,alpha_2,beta_2 : IN STD_LOGIC_VECTOR (11 downto 0);
CLK,reset : IN STD_LOGIC;
SI : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
carry_out : OUT STD_LOGIC
);
END similarity_indicator;

architecture struct of similarity_indicator IS

--signal declaration
Signal mult1_a, mult1_b, mult2_a, mult2_b, sqrt1_output, sqrt2_output, adder1_a, adder1_b, adder1_result, adder2_a, adder2_b, adder2_result,t1 : STD_LOGIC_vector (11 downto 0);
Signal mult1_result, mult2_result, sqrt1_input, sqrt2_input : STD_LOGIC_vector (23 downto 0);
Signal adder1_carryout, adder2_carryout : STD_LOGIC;
Signal sqrt1_remainder, sqrt2_remainder :STD_LOGIC_VECTOR (12 downto 0);

--state definition
Type state is (one, two, three, four, five, six, seven, eight);
Signal present_state, next_state :state ;


--multiplier declaration

COMPONENT lpm_mult
GENERIC (
lpm_hint : STRING := "DEDICATED_MULTIPLIER_CIRCUITRY=NO,MAXIMIZE_SPEED=5";
lpm_representation : STRING := "UNSIGNED";
lpm_type : STRING :="LPM_MULT" ;
lpm_widtha : NATURAL :=12 ;
lpm_widthb : NATURAL :=12 ;
lpm_widthp : NATURAL :=24
);
PORT (
dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
);
END COMPONENT;

--square root unit declaration

COMPONENT altsqrt
GENERIC (
pipeline : NATURAL :=3;
q_port_width : NATURAL :=12;
r_port_width : NATURAL :=13;
width : NATURAL :=24;
lpm_type : STRING :="altsqrt"
);
PORT (
remainder : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
radical : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
clk : IN STD_LOGIC
);
END COMPONENT;

-- adder declaration

COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING := "ADD";
lpm_hint : STRING := "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO" ;
lpm_type : STRING := "LPM_ADD_SUB";
lpm_width : NATURAL := 12
);
PORT (
dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
cout : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END COMPONENT;

Begin
--portmapping of blocks

-- portmapping the multipliers
multiplier1:lpm_mult port map (mult1_a, mult1_b,mult1_result);
multiplier2:lpm_mult port map (mult2_a, mult2_b,mult2_result);

--portmapping the square root units
sqrt1:altsqrt port map (sqrt1_remainder,sqrt1_input,sqrt1_output,CLK);
sqrt2:altsqrt port map (sqrt2_remainder,sqrt2_input,sqrt2_output,CLK);

--portmapping the adder units
adder1:lpm_add_sub port map (adder1_a, adder1_b,adder1_carryout ,adder1_result);
adder2:lpm_add_sub port map (adder2_a, adder2_b,adder2_carryout ,adder2_result);

--process part
statesrocess (present_state)
Begin

--switch on the possible states to producs the required FSM
CASE present_state IS
WHEN one =>
mult1_a <= alpha_1;
mult1_b <= beta_1;
mult2_a <= alpha_2;
mult2_b <= beta_2;
next_state <= two;

WHEN two =>
mult1_a <= alpha_1;
mult1_b <= beta_1;
mult2_a <= alpha_2;
mult2_b <= beta_2;
sqrt1_input <= mult1_result;
sqrt2_input <= mult2_result;
next_state <= three;

WHEN three =>
mult1_a <= alpha_1;
mult1_b <= beta_1;
mult2_a <= alpha_2;
mult2_b <= beta_2;
sqrt1_input <= mult1_result;
sqrt2_input <= mult2_result;
next_state <= four;

WHEN four =>
sqrt1_input <= mult1_result;
sqrt2_input <= mult2_result;
next_state <= five;

WHEN five =>
adder1_a <= sqrt1_output;
adder1_b <= sqrt2_output;
next_state <= six;

WHEN six =>
t1 <= adder1_result;
adder1_a <= sqrt1_output;
adder1_b <= sqrt2_output;
next_state <= seven;

WHEN seven =>
adder2_a <= t1;
adder2_b <= adder1_result;
adder1_a <= sqrt1_output;
adder1_b <= sqrt2_output;
next_state <= eight;

WHEN eight =>
adder1_a <= adder1_result;
adder1_b <= adder2_result;
SI <= adder1_result;
carry_out <= adder1_carryout;
next_state <= one;

end CASE;
end process;
seq: Process (CLK, reset)
Begin
If (reset = '0') THEN
present_state <= one;
ELSIF (CLK'EVENT AND CLK = '1') THEN
present_state <= next_state;
END IF;
END process;

end struct;

 

[TrickyDicky]

THe main problem will be that in your asynchronous state machine you have not assigned all signals in all cases. This means you are creating latches (Which are bad) for many of your signals.

 

[fpgadsgnr]

i would be really grateful if someone could tell me what is wrong with this code



LIBRARY LPM;
USE LPM.LPM_COMPONENTS.ALL;
LIBRARY work;
USE work.ALL;

Have you added packages in your project that you are using here? Also can you share the synthesis report and resource usage?

Thanks,
Fpgadsgnr

 

[TrickyDicky]

The LPM library is part of the Altera libraries.