how to compile test bench on iverilog compiler over linux environment

[shiven]

i had written following simple verilog code of and gate and its test bench and m using iverilog compiler over linux

main module:

module AND(y,a,b);
output y;
input a,b;
and(y,a,b);
endmodule

test bench:

module testAND;
wire y;
reg a,b;
AND (y,a,b);
initial
begin
a=0;b=0;
#5
a=0;b=1;
#5
a=1;b=0;
#5
a=1;b=1;
end
endmodule
problem is that main module gets compiled properly but when i compile test bench it throws following error msg

:~/Desktop/verilog$ iverilog -o test tand.v
tand.v:5: error: Unknown module type: AND
2 error(s) during elaboration.
*** These modules were missing:
AND referenced 1 times.
***
please tell me how to overcome this as soon as possible i am waiting for help

 

[kingslayer]

Hi,

there is an error in the creation of the AND instance: you should define both the instance name and the instance module as follows:

AND myAND(y, a, b);

Try this way and get us back!

Cheers

 

[shiven]

its still throwing the same message i tried the same code over modelsim on windows its working could you please help me on this

 

[fpgadsgnr]

i had written following simple verilog code of and gate and its test bench and m using iverilog compiler over linux


problem is that main module gets compiled properly but when i compile test bench it throws following error msg

:~/Desktop/verilog$ iverilog -o test tand.v
tand.v:5: error: Unknown module type: AND
2 error(s) during elaboration.
*** These modules were missing:
AND referenced 1 times.
***

Try following command and let me know if it works.

iverilog -o test tand.v test.v

Thanks,
Fpgadsgnr