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Recent content by endru

  1. E

    Native transistor for op amp

    Hi guys, I would like to use native transistor for my op amp. Has anyone done this before? What are the things that I need to take care? Thanks in advance!
  2. E

    noise of pmos and nmos

    why pmos is preferred over nmos Hi ieropsaltic, May I know why higher gm is preferred regarding the input-referred noise of amplifier, while lower gm is preferred for current mirror? Thanks!
  3. E

    Loop stability in low dropout regulators

    Re: LDO stability Maybe what he means is to use replica biasing for the output transistors, just like what these papers do: - Embedded 5 V-to-3.3 V Voltage Regulator for Supplying Digital IC’s in 3.3 V CMOS Technology <-- this guy used NMOS, instead of PMOS - Area-Efficient Linear Regulator...
  4. E

    LDO thermal shutdown circuite

    bjt with thermal shutdown If you really want to use 2 VBE, maybe you can try this:
  5. E

    OP-amps topologies tradeoffs

    You can refer to this topic:
  6. E

    Temperature Coefficents of a resistor....

    You can find them in the design rule manual. If you don't have, you can get it through simulation. Just bias the resistor with constant current source, without any DC voltage, and simulate it over temperature. Then you plot the voltage across it. You will see, how the voltage change over...
  7. E

    Lowest mismatch variation bandgap?

    Thanks a lot guys! I agree with you. I also found that if we stack the BJTs, the mismatch effect can be reduced. But of course with the trade-off of area..
  8. E

    Four questions about bandgap circuit design

    Re: Bandgap Problem!! Just want to add, for question 1: the higher the ratio, the better it is (to minimize VBG variation due to mismatch). Because if there is an offset within your opamp or any device which make sure that the voltages between the two branches are the same (if you use that...
  9. E

    Lowest mismatch variation bandgap?

    bandgap design npn Hi, Can anyone suggest me, which bandgap architecture that gives the lowest variation due to mismatch? Any paper? Thanks.
  10. E

    how to get high psrr for BGR

    For DC, you can boost PSRR by adding an opamp into the loop. For high freq, you can put a cap between the PMOS current mirror's gate to VDD (if you use PMOS current mirror to distribute the current). For VDD PSR, is it better to use PMOS input opamp? Anyone knows? Thanks.
  11. E

    Which one is better, voltage-mode or current-mode bandgap?

    voltage mode and current mode Hi all, As we know, we can make a bandgap circuit using either voltage-mode or current-mode approach. Suppose that I use the architecture that has an opamp pointing upwards with two PMOS on its right and left branch, which mode should I work on if I want to have...
  12. E

    comparison of two LDO structures !!

    Yes, A is better. The output transistor normally has large VGS swing as it is required to drive output current from 0 to some tens or hundreds mA. Therefore, when your output current is 0, the output transistor's gate-source voltage will be very small. Hence structure B is not suitable...
  13. E

    Why do we need a start up circuit for this bandgap?

    Re: bandgap start up Hi saro_k_82, Can you explain further why: - the mismatch performance is poor? - stability at the working region is poorer than it is at zero-state? - stability is further degraded by connecting the follower to R2 instead of R3? Thanks in advance!
  14. E

    Questions about the function and characteristics of RHP pole

    rhp pole unstable I see... But, could you explain me why the system is still unstable although it locates beyond the UGF? Thanks in advance!
  15. E

    Questions about the function and characteristics of RHP pole

    rhp pole compensation Ups.. sorry, I mean this is the bode plot of the whole LDO, not just the err amp. I got this by tapping from the feedback point. Any opinion? Thanks!
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