Why do we need a start up circuit for this bandgap?

[endru]

Re: bandgap start up

Hi saro_k_82,

Can you explain further why:
- the mismatch performance is poor?
- stability at the working region is poorer than it is at zero-state?
- stability is further degraded by connecting the follower to R2 instead of R3?

Thanks in advance!

 

[saro_k_82]

Re: bandgap start up

1. This architecture is known to have poor mismatch performance when compared to other known high-supply text-book BGR architectures. I said it is not advisable at 3.3V supply. When the supply is only 1.2V and you are willing to spend a lot of area, it's blemishes are erased.
Small mismatches between the two PMOS can lend the circuit unstable(Unless you have a really huge device so that it's 3-sigma mismatch is taken care of). Refer to this topic too...

2. Try computing the beta of the loop in the zero current state (The amp is PMOS and it is ON). As the diodes are off, beta is close to 1 (I have taken the PMOS also as part of the amp). It needs some small mismatches to be stable. But when it is stable, all nice properties of negative feedback., viz offset, CMRR, PSRR are going to be better than when it is working in the intended state. It takes a much bigger disturbance to make it come out of it's state there.

3. Any cap at R2 (either to VDD or GND) is going to rob the current that should have passed through R1. R1 is solely responsible for stability. In simple terms the negative feedback beta is reduced. But if you connect the amp to R3, the cap there will decrease positive feedback beta which enhances the stability.

Thanks,
Saro

 

[xuedashun]

bandgap start up

i think the two amp input connections are wrong

 

[standup]

Re: bandgap start up

I think the inputs of the amplifier are connected incorrectly,this is a positive feedback loop.

 

[skung]

Re: bandgap start up

i think the two amp input connections are wrong

Hi Xuedashun,
Could you explain why you think the two amp input connections are wrong?
I can see the main amp in the middle of the circuit is wrong. Can you also
help explain how the main one is wrong from your point of view?

Thanks.

siu