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Recent content by craftfox

  1. C

    [REQ] Protel 99SE compatible libraries for Spartan3 FPGA

    Hello: Who has the Protel 99SE compatible libraries for the Spartan3 FPGA and XCF family Flash memory? Symbol Library and Footprint Library are both needed! thanks!
  2. C

    [REQ] Protel 99SE Spartan3 compatible libraries

    Hello: Who has the Protel 99SE compatible libraries for the Spartan3 FPGA and XCF family Flash memory? Symbol Library and Footprint Library are both needed! thanks!
  3. C

    Want to find useful thesis or source code for AES cipher

    Hi all, I am searching for verilog source code of the new cryptographic block cipher AES in the field of reconfigurable computing (especially FPGAs) . I have a huge interest in AES, but the problem that thousands of researches are done in this field, so I am trying to find something new that's...
  4. C

    64 0r 128 carry select adder

    you can try this link: I have uploaded a phd thesis. it included comprehensive arithmetic of carry select adder. If you are chinese, i can also sell one commercial adder ip core to you.
  5. C

    Tips for implementing cryptosystems on FPGA

    Crypto on FPGA the IP of opencore site is too simple to use in practice. if u want to develop a cryptosystem, i think u can find some good papers on the google.
  6. C

    How to configure the LUT?

    how to configure the LUTs as ROM? how to configure the LUTs as shift register? Can you give me some paper/example/code? Are these tasks done by hand? or by the develop software?
  7. C

    what's the format of the bitsream?

    This project has one special object: to research all the possible methods to secure the FPGA design. I think that the bitstream is the IP of the source desinger, so the secure of it will promise the security of the FPGA design. But all the company have not give the format of their FPGA publicly.
  8. C

    what's the format of the bitsream?

    I will do a project to secure configuration for the FPGA. Now i want to use the partial-encryption technique, so i want to find the real format of the bitstream file. Can you give me some advice, some useful link/page/paper/thesis/, and so on? thanks you a lot!! craftfox
  9. C

    How to design a 64bit adder in VHDL?

    adder your can design it at gate level. i.e. use the "or" logic\"xor"logic\"and" logic. I completed one 64-bits signed adder last month using the verilog. I think it's easy to transfer it into VHDL code if you like to. ps you can not find the existing one on the internet. so read the article...
  10. C

    Resources about designing 128 bit adders

    Re: 128 bit adders ok! please enjoy this phd thesis. It will give your great help!
  11. C

    'signal' (vhdl) = 'wire' or 'reg' (verilog)

    verilog wire reg I think u have had a vhdl version in your hand. You can analysis the function of the vhdl module. None fixed relation.
  12. C

    software do simulate FPGA design

    The ActiveHDL will be better than Modelsim if the design project not using the BlockRam in FPGA.
  13. C

    Separate Big FSM into Small FSMs

    Your teacher just wanted you to divided big fsm into several small fsm. His main idea is put the small fsm into the right small component. It will simpler your design.
  14. C

    two question about 4:2 compressor verilog module

    I have finished this project. Thanks for your help! You know, i think i use the right method. When use the [4-2] counter, you must absorbing the last bit position's cout signal.
  15. C

    two question about 4:2 compressor verilog module

    if i use a [4-2] counter at 12th bit position, the cout signal will be discarded. I think it isn't right . I think i must use a [4-2] counter with 3 inputs at 13th bit position absorbing the 12th cout singal. Is it right??
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