two question about 4:2 compressor verilog module

[craftfox]

verilog compressor

i just want to know how to deal with the cin singal of the first 4:2 compressor, set it to zero?

another question: when the consecutive high bit position (j+1) is a CSA,how to deal with the cout singal of the current bit position(j)'s 4:2 compressor, just discards it?

 

[eda_wiz]

Compressor is designed so that cout is not a function of cin to avoid ripple-carry effect

c the attach

read this page
https://www.geoffknagge.com/fyp/carrysave.shtml

Ur second question is not clear.

 

[craftfox]

i read this page,but i still don't know how to deal with the fist cin signal and the last cout signals. I write a picture to describe my question.

 

[eda_wiz]

you can ground the first cin signal or use just a full adder since not all 4 bits are present. the last cout pin can be discarded as it does not change any significant bits in the product.

 

[craftfox]

if i use a [4-2] counter at 12th bit position, the cout signal will be discarded. I think it isn't right . I think i must use a [4-2] counter with 3 inputs at 13th bit position absorbing the 12th cout singal. Is it right??

 

[craftfox]

I have finished this project. Thanks for your help!
You know, i think i use the right method. When use the [4-2] counter, you must absorbing the last bit position's cout signal.