'signal' (vhdl) = 'wire' or 'reg' (verilog)

[davyzhu]

vhdl wire

Hello all,

I found vhdl use signal and verilog use wire and reg to describe a connection between combinational logic, but the thing bothered me that "how to specify the signal to be wire or reg" or " signal equal to wire or reg" ? :roll:

Regards,

Davy Zhu

 

[eda_wiz]

vhdl reg

davyzhu..
I guess u r trying to convert some VHDL to verilog. Well a signal in VHDL can be reg or wire in verilog.. ie if the signal is intended to be synthesised as a flop .. it shud be reg... else wire...
Inside the "process" statement , if any signal is assigned to any other signal it will be flop .. or if outside process it will be a net..

hope this helps

 

[craftfox]

verilog wire reg

I think u have had a vhdl version in your hand. You can analysis the function of the vhdl module. None fixed relation.

 

[presto]

verilog reg in vhdl

davyzhu..
I guess u r trying to convert some VHDL to verilog. Well a signal in VHDL can be reg or wire in verilog.. ie if the signal is intended to be synthesised as a flop .. it shud be reg... else wire...
Inside the "process" statement , if any signal is assigned to any other signal it will be flop .. or if outside process it will be a net..

hope this helps

regards
WHIZKID

In Verilog, 'reg' does not have to be synthesised as flop or latch, even when it's in the 'always' statement. Also, I wondered if 'signal' in the 'process' in VHDL was always synthesised into flop or latch? As I just started to use VHDL, will any VHDL guru clarify this point? cheers

 

[bibo1978]

wire in vhdl

I believe that there is no straight forward relation however, I yoou can use this rule, if the signal is synthesized as a register or latch, then use reg otherwise use wire, I believe it is this simple.

However Iwant to note that not all process in VHDL produce a reg. or latch but it depends on two things, 1- the sensitivity list, 2- wether all conditions of changes were included in the process code area.


thats all folks