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Recent content by Blowfishie

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    Lets talk about pin multiplexing

    Are you looking for an automated check or will manual do? A manual check is to open your synthesised design in the vendor's FPGA editor tool and drill down into the logic to see if it has been synthesised as you expect. If you're looking for automated, I'd write a Perl script (or similar) to...
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    How to protect VHDL source code?

    Re: VHDL Code Protection This only works if both parties are using the same version of ModelSim.
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    How to protect VHDL source code?

    Re: VHDL Code Protection If you are both using ModelSim, you can take a look at Chapter 3 of the user manual (here) to read about encrypted source. **broken link removed** There's another thread here for a similar topic: https://www.edaboard.com/threads/220638/
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    Query in multiple clockdomain

    Some cases: Case 1: Single signal crossing clock domains, toggling slowly (i.e. not a pulse). Use 2 flip-flops to re-time it into the new clock domain Case 2: Single signal crossing clock domains, pulsing for 1 clock cycle in the original domain. Convert the pulse into a toggled signal, pass...
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    Xilinx ISE Coregenerator...is it really usefull?

    Take the case of writing a FIFO. You can write your own, for sure, but why bother when the Coregen wizard just asks you for the FIFO's design parameters and creates something that works right away. You may be able to make a more optimised design. You can directly instantiate primitives in...
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    Help me do some fractional arithmetic using VHDL

    Re: Fractional Arithmetic Here is a good introduction (with worked examples) to using fixed-point arithmetic: https://cnx.org/content/m11054/latest/
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    Need Sprten-3 IBIS model

    Re: Need Spartan-3 IBIS model Here's a direct link to the file... **broken link removed**
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    how to synchronize multiple operations on a vector(signal)

    Re: how to synchronize multiple operations on a vector(signa Or just do it in one line: r3 <= r1(1 xor r2(21) xor ref_vec (63) & r3(22 downto 1); Added after 13 minutes: Actually, in this case you aren't. If you assign a value to a signal, then re-assign it later on in the same process...
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    What is the exact simulation flow of a Verilog code?

    Re: simulation flow If you are looking for an explanation of 'delta time', have a look here: **broken link removed**
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    VHDL code for digital CDR

    Re: CLock Data Recovery Interestingly, Xilinx have just updated their data recovery app note. XAPP224 - Data Recovery https://www.xilinx.com/bvdocs/appnotes/xapp224.pdf I know you're not after Xilinx, but the principles involved should be similar.
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    Need multiplier function for Spartan 2E

    Use the CoreGen application in ISE to create a multiplier, then drop it into your code as a "black box" component.
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    Question about Xlinx Timing Constrain

    EDALIST's answer sounds right, but if you want to understand timing constraints and errors, I have just the thing for you... Here is a link to a SUPERB document describing static timing in Xilinx devices, how to set up constraints and what they do. It also covers the error messages and the...
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    self synchronous scrambler - VHDL

    scrambler.vhd The reason that it's not descrambling properly is that the value in the descrambler's shift-register is 1 clock cycle ahead of the scrambler's one. Effectively the descrambler is descrambling at the wrong point in time. You should try to introduce some method of synchronisation...
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    FPGA configured with PROM

    A quote from Xilinx User Guide ug161 (Platform Flash PROM User Guide): The FPGA has an on-board oscillator for configuration use only.
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    Xilinx ISE and included programs

    To summarise... Architecture Wizard: A quick point and click way to generate HDL for the DCMs and RocketIOs Chip Viewer: A version of FPGA Editor for CPLDs Constraints Editor: A helper for writing your UCF files Core Generator: A wizard interface for Xilinx (and 3rd party) IP Floorplanner...
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