Lets talk about pin multiplexing

[user_asic]

Guys,

When doing multi-FPGA designs, there are times you (or the CAD tool) inadvertently adds a non multi-cycle net or combinational net through time division multiplexing (TDM) logic after partitioning. Adding such nets to TDM logic may lead to incorrect operation. What are some of the techniques you use to detect these mistakes?

uA

 

[Blowfishie]

Are you looking for an automated check or will manual do?

A manual check is to open your synthesised design in the vendor's FPGA editor tool and drill down into the logic to see if it has been synthesised as you expect.

If you're looking for automated, I'd write a Perl script (or similar) to parse out the mapped netlist.