What is the exact simulation flow of a Verilog code?

[s_vlsi]

I want to know the exact simulation flow ,i.e. when we simulate a verilog code
what is the exact simulation flow? Which events occur?
can anyone provide me with the link

Thanks

 

[Blowfishie]

Re: simulation flow

If you are looking for an explanation of 'delta time', have a look here:
**broken link removed**

 

[aji_vlsi]

Re: simulation flow

I want to know the exact simulation flow ,i.e. when we simulate a verilog code
what is the exact simulation flow? Which events occur?
can anyone provide me with the link

Thanks

Do you want to understand "simulator's event queue" mechanism? If so, best bet is to read LRM (Verilog/SV) on Stratified event queue. It takes a while to grasp it, but well explained in it.

Instead if you are looking for "how my simulation flows through" - you Verification architecture should tell you that. A typical flow is like:
reset, configure, run some testvectors, wait for end, report and finish.

And this is where a standard verification methodology such as VMM comes in very handy. See www.vmm-sv.org for more. Also see my new book mentioned below in the signature, we devoted few sections on this very topic.

BTW, a similar flow implemented in E language is available from www.aceverifciation.com for download.

HTH,
Ajeetha, CVC
www.noveldv.com
New Book: A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
https://www.systemverilog.us/