how to synchronize multiple operations on a vector(signal)

[s3034585]

hi guys
i have a dought on how to perform multiple operations on a vector which is declared as signal in a architecture.

to give a clear idea the code is as follows;

if ( clk'event and clk ='1') then
if (load = '0' and load_r ='1') then
r3(22) <=r1(18) xor r2(21) xor ref_vec (63);
r3 <= r3(21 downto 0) & '0';
elsif (c3 = c1) or (c3 = c2) then
r3(22) <= r1(18) xor r2(21) xor ref_vec (63);
r3 <= r3(21 downto 0) & '0';
r3(2) <= x xor y;
end if;

i know it wont work properly because i am refering to the new value in the signal even before it is updated as it is a signal. i want to perfrom these operations one clock cycle so what is the best way to do it. becaues there are 2 left shift registers also which are updated along with r3 in the same clock cycle. but as now some addition operations has to be done on r3 how can i manage to do in the same cycle so that it is in synch with other registers....


if any further clarification is required please let me know.

thanks in advance for your help.
tama

 

[EDALIST]

Re: how to synchronize multiple operations on a vector(signa

you are making a contention :
r3(22) <=r1(1 xor r2(21) xor ref_vec (63);
r3 <= r3(21 downto 0) & '0';

if r3 is 22..0

then you need to do

r3(22) <=r1(1 xor r2(21) xor ref_vec (63);
r3(21 downto 0) <= r3(22 downto 1);
carry_out <= r3(0); -- if you need it.
-- so here you have a right way shift register

 

[Blowfishie]

Re: how to synchronize multiple operations on a vector(signa

Or just do it in one line:

r3 <= r1(1 xor r2(21) xor ref_vec (63) &  r3(22 downto 1);

Added after 13 minutes:

you are making a contention

Actually, in this case you aren't.

If you assign a value to a signal, then re-assign it later on in the same process, the latter assignment is the one that is used. I often use this technique in state machines to ensure that pulsed signals are cleared when they are not explicitly set. I assign the pulsed signal to '0' at the top of the state machine, then somewhere in the state machine logic, I set it to '1'. When the '1' condition is not true, I can guarantee that the value is a '0'.

If you have two separate processes and you assign something to the same signal, then you get contention.

Also, if you make 2 asynchronous assignments outside of a process (within the architecture block), then you also get contention.

 

[tkbits]

Re: how to synchronize multiple operations on a vector(signa

You can also use auxiliary signals to keep it in parts.

value1 <= r3(21 downto 0) & '0';
value2 <= (r1(18) xor r2(21) xor ref_vec(63)) & value1(21 downto 0);
value3 <= value2(22 downto 3) & (x xor y) & value2(1 downto 0);

process (clk)
begin
  if ( clk'event and clk ='1') then
    if (load = '0' and load_r ='1') then
      r3 <= value2;
    elsif (c3 = c1) or (c3 = c2) then
      r3 <= value3;
    end if;
  end if;
end process;