[SOLVED] Multiple driver issue

[Digistu01]

Hi ,
I am working in verilog.
I have an incoming signal to my fpga and one out signal. when this incoming goes high, I want the output signal to go low and stay low for 1000 clk cycles, irrespective of if the incoming signal goes low/ high. The code synthesises correctly but gives me multiple driver error when I implement it, which I clearly see . I know I cannot drive the reg “ temp” in two different always blocks . But how can I resolve this issue.
Following is the code :

---

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module driver_low
 input en,
 output wire reg_out_pin
);
 
reg [9:0] count;
reg temp;
reg reg_out;
 
assign reg_out_pin = reg_out;
 
always @( posedge en) begin
   temp <= 1’b1;
end
 
always @( posedge clk) begin
       If( temp) begin
           If ( count <= 10’d1000)
                 reg_out <= 1’b0;
           else begin
                 reg_out <= 1’b1;
                 temp <= 1’b0;
                 count <= 10’d0;
           end    
     end
          reg_out <= 1’b1;
end

---

 

[FvM]

Besides the multiple driver problem, the code
- doesn't count
- sets output unconditionally high

posedge(clk) models synchronous logic with DFF. A DFF can have only one clock input.

Simple solution would be synchronous edge detection.

reg [2:0] sync;
always @( posedge clk) begin
    sync <= {sync[1:0], en};
    if (sync[2:1] = 2'b01) //  rising en edge
        temp <= 1'b1;
end;

 

[Digistu01]

Besides the multiple driver problem, the code
- doesn't count
- sets output unconditionally high

posedge(clk) models synchronous logic with DFF. A DFF can have only one clock input.

Simple solution would be synchronous edge detection.

reg [2:0] sync;
always @( posedge clk) begin
    sync <= {sync[1:0], en};
    if (sync[2:1] = 2'b01) //  rising en edge
        temp <= 1'b1;
end;

Thanks!