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Recent content by aeneas81

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    [Quartus II] How to hold a process for a specific time

    [qu@rtus II] How to hold a process for a specific time wow, thanks for the code, wasp. i've tried using the counter version as mentioned by r_e_m_y, though it works fine, I am just wondering is there any other option to achieve the same thing, using less code. anyway, thanks a lot.
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    Help me fix a code for calculating crc-5 of 11 bit data

    need help with this, pls hi, thanks for reply and the code supplied. however, i do have a question in mind, if process it in counter based, wouldn't it takes decades? i really hope it could be done asap coz sometimes much more than 11 bits will be processed, sometimes up to a few KB... and my...
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    Help me fix a code for calculating crc-5 of 11 bit data

    need help with this, pls Dear all, I've written the following process to calculate the crc-5 of an 11 bit data for usb purpose. it takes one data at a clock cycle and stores to a signal, then at the 12 clock cycle will perform the calculation. however, for some unknown reason, quartus II keep...
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    [Quartus II] Ignored default value

    [qu@rtus II] Ignored default value Thanks... I'm using VHDL in Altera Quartus II ver4.0
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    [Quartus II] Ignored default value

    ignored default value for signal Dear all, I'm wondering why is the default value assign to a signal is always ignored? Is there any special constraints to assign a default value to a signal? All I want to do is to assign a default value to a signal and use that value until external input...
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    [Quartus II] How to hold a process for a specific time

    Hi all, How can I check that a signal holds it's value for a specific period, such as 5ms, using VHDL in Quartus II? I tried to use Wait for, after simulation, that doesn't has any effect at all. Hope that any of you would be able to help. Thanks in advance Rgds, aen
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    Help me make a clock divider in VHDL using Altera FPGA

    clock divider Dear all, I would to write a PLL kind of stuff using VHDL using @ltera fpga, and would sincerely appreciate any ideas on doing it. I'm trying to derive a 12MHz clock from a 48Mhz clock. The 12MHz clock will only start generating once a predefined input sequence pattern has been...
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    Pins that function as both inputs and outputs

    cube, u really made my day!!! thank you so much!! finally i managed to solve a large problem with my design. Thanks! n god bless :)
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    Pins that function as both inputs and outputs

    I've found the answer myself. Thanks a lot! The std_ulogic type This type is used to represent the value of a digital signal in a wire. For general use, you probably want the std_logic instead. A signal or variable of this type can take on the following values: 'U': uninitialized. This...
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    Pins that function as both inputs and outputs

    thanks dude, i'll try on the code. by the way, what's a std_ulogic type?
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    Pins that function as both inputs and outputs

    Dear all, could anyone please teach me how to create pins that can be use as input pin as well as output pin (in VHDL)? I've tried using: twowayPin : INOUT std_logic_vector(63 DOWNTO 0); but whenever i compile i got the follwing warning: Warning: TRI or OPNDRN buffers permanently enabled and...
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    Critical Warning: Timing requirement not met

    Re: Critical Warning Problem Does that means it processes too many signals in one clock cycle? bsides, I only supplied a 48MHz clock, how come it requires 180MHz instead?
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    Critical Warning: Timing requirement not met

    Re: Critical Warning Problem This is a print screen of my error, really appreciate help from any of you all. I have been stucked here for quite sometime and couldn't figure out how to solve this problem... Rgds
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    Critical Warning: Timing requirement not met

    Critical Warning Problem Dear All, Whenever I compile my project(written in pure VHDL codes), it displays a "Critical Warning: Timing requirement not met" and "Can't achieve minimun setup and hold requirement clk along (some numbers) of path(s)" Could anybody please explain to me what this...
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    Display array data according to clock pulse

    Don't quite understand what do you mean by display, if you wish to output an array at once, maybe you can try this: assuming you have an output pin: display_array : OUT std_logic_vector(your array size) then declare a signal: SIGNAL array_count : INTEGER PROCESS(clk) BEGIN IF clk'EVENT...
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