Help me fix a code for calculating crc-5 of 11 bit data

[aeneas81]

need help with this, pls

Dear all,
I've written the following process to calculate the crc-5 of an 11 bit data for usb purpose. it takes one data at a clock cycle and stores to a signal, then at the 12 clock cycle will perform the calculation. however, for some unknown reason, quartus II keep synthesized away my registers, and i couldn't get the correct output.
btw, i've read from book that variables does not hold it's value as signals do, but I've seen codes with variables that can hold its value over clock edge just like signal does, how come?
Thanks for your help and advice.


the crc-5 code i'm working on:


SIGNAL stuffed_dataSig : std_logic_vector(10 DOWNTO 0);

process (clk, rst, din)
variable stuffed_data : std_logic_vector(10 DOWNTO 0);
variable crc5_state : std_logic_vector(4 DOWNTO 0);

begin

if rst = '1' then

count <= 0;

out_crc5 <= "11111";

stuffed_dataSig <= "00000000000";

ELSIF clk'EVENT AND clk = '1' THEN

IF count < 11 then
-- get the input data
stuffed_dataSig(count)<= din;
count <= count+1;

-- to verify that data is being stored
testout <= stuffed_dataSig;

ELSIF count = 11 THEN -- calculate crc
stuffed_data := stuffed_dataSig;
crc5_state := "11111";

for i in 0 to 10 loop

crc5_state(0) := stuffed_data(i)xor crc5_state(4);
crc5_state(1) := crc5_state(0);
crc5_state(2) := crc5_state(1)xor crc5_state(4)xor stuffed_data(i);
crc5_state(3) := crc5_state(2);
crc5_state(4) := crc5_state(3);

end loop;

out_crc5 <= NOT crc5_state;

end if;

end if;

end process;

 

[r_e_m_y]

Re: need help with this, pls

Hi,

The problem of your algorithm, is thatyou try to calculate the CRC in a for loop at the end of the count process.
Your loop shall not be done with a for instruction (as in software) but in the counter loop. So at each clock cycle, the CRC5 value is elaborated. At the end of the counter (=11) your value is ready and can be output for use.

Do not use variable in synthesisable vhdl : your functional simulation (with modelsim for ex) will represent your design, and not a SW code evaluation...

try a code that looks like :
SIGNAL stuffed_dataSig : std_logic_vector(10 DOWNTO 0);
SIGNAL crc5_state : std_logic_vector(4 DOWNTO 0);

process (clk, rst, din)

begin

if rst = '1' then

count <= 0;
crc5_state <= "11111";
out_crc5 <= "11111";

ELSIF clk'EVENT AND clk = '1' THEN

IF count < 11 then
count <= count+1;

crc5_state(0) <= din xor crc5_state(4);
crc5_state(1) <= crc5_state(0);
crc5_state(2) <= crc5_state(1)xor crc5_state(4) xor din;
crc5_state(3) <= crc5_state(2);
crc5_state(4) <= crc5_state(3);

ELSIF count = 11 THEN -- calculate crc

out_crc5 <= NOT crc5_state;

end if;

end if;

end process;

PS : I did not try this code...

Hope this will help you :wink:

 

[aeneas81]

need help with this, pls

hi,
thanks for reply and the code supplied.
however, i do have a question in mind, if process it in counter based, wouldn't it takes decades? i really hope it could be done asap coz sometimes much more than 11 bits will be processed, sometimes up to a few KB... and my program couldn't afford that much time as there are other process to be run after crc has been generated. Thanks for your valuable advice

Rgds

 

[r_e_m_y]

Re: need help with this, pls

Hi,

in fact, the CRC calculatuion will be performed in the data flow. At each clock cycle, you've got a new data, and at each clock cycle, this data is taken into account in the CRC calculation.
In your previous code, you still have a counter which only counts during 11 clock cycles, then in 1 clock cycle, try to calculate the CRC (with bad coding).

It should take the same time...