aeneas81
Junior Member level 1
Dear all,
could anyone please teach me how to create pins that can be use as input pin as well as output pin (in VHDL)? I've tried using:
twowayPin : INOUT std_logic_vector(63 DOWNTO 0);
but whenever i compile i got the follwing warning:
Warning: TRI or OPNDRN buffers permanently enabled
and the default signal has become all ZZZZZZZZZZZ
if i try to simulate a data input, it will give a warning that signal contention happens..
pls help pls help... thank you very much
could anyone please teach me how to create pins that can be use as input pin as well as output pin (in VHDL)? I've tried using:
twowayPin : INOUT std_logic_vector(63 DOWNTO 0);
but whenever i compile i got the follwing warning:
Warning: TRI or OPNDRN buffers permanently enabled
and the default signal has become all ZZZZZZZZZZZ
if i try to simulate a data input, it will give a warning that signal contention happens..
pls help pls help... thank you very much