aeneas81
Junior Member level 1
Hi all,
How can I check that a signal holds it's value for a specific period, such as 5ms, using VHDL in Quartus II?
I tried to use Wait for, after simulation, that doesn't has any effect at all. Hope that any of you would be able to help. Thanks in advance
Rgds,
aen
How can I check that a signal holds it's value for a specific period, such as 5ms, using VHDL in Quartus II?
I tried to use Wait for, after simulation, that doesn't has any effect at all. Hope that any of you would be able to help. Thanks in advance
Rgds,
aen