Critical Warning: Timing requirement not met

[aeneas81]

Critical Warning Problem

Dear All,
Whenever I compile my project(written in pure VHDL codes), it displays a "Critical Warning: Timing requirement not met" and "Can't achieve minimun setup and hold requirement clk along (some numbers) of path(s)"

Could anybody please explain to me what this means and how to solve the problem? My project only consists of conventional if - else, case and for loop...

Sincere thanks to all of you.

Rgds

 

[aeneas81]

Re: Critical Warning Problem

This is a print screen of my error, really appreciate help from any of you all. I have been stucked here for quite sometime and couldn't figure out how to solve this problem...


Rgds

 

[echo47]

Critical Warning Problem

The software is telling you that the routed design won't work at your requested clock rate (180 MHz). Looks like you need to either slow down the clock, or break up your design into simpler pipeline stages.

Goog luck!

 

[aeneas81]

Re: Critical Warning Problem

Does that means it processes too many signals in one clock cycle? bsides, I only supplied a 48MHz clock, how come it requires 180MHz instead?

 

[Buriedcode]

Re: Critical Warning Problem

Hi, I'm no expert but I've had unpleasant dealings with simiilar software before.

The '180MHz' is whats called FMAX. This is the maxaimum clock that can be supplied to the device without it screwing up. The problem is that whenever you route a signal through gates/flipflops, there is some small delay, its tiny, but at high frequencies it can approach the actual period of the Clock.

So, Echo's advice is spot on 8)

The delay between some of the input signals and output signals of your design is larger than the period of 180Mhz (5.5ns I believe).
This is fine if you're running it from a 48Mhz clock.
But, if you want to make it able to run faster, you must reduce the number of gates/flipflops between the inputs and the outputs, by 'breaking up' the design.

I didn't look at the screenshot, but I assume you've got some setting which, when it partitions the design, is trying to make it run at FMAX, which it can't. Try removing some global constraints regarding speed.

Hope this helps,

BuriedC+ode