Zero WLM Analysis in RTL Compiler (RC 12.20)

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spgite

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I am trying to do zero wlm analysis.
But in the reports its not showing any wireload model being used
In library there was no wireload model so I have defined one.

Need to know the commands to include wireload model

Thank you
 

Following attributes of RC can help in doing ZWLM synthesis or WLM synthesis

1) interconnect_mode
2) wireload_selection
3) force_wireload

Hope this can help you..

~vamsi
 
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Thank you for reply..
 

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