Zero WLM Analysis in RTL Compiler (RC 12.20)

[spgite]

I am trying to do zero wlm analysis.
But in the reports its not showing any wireload model being used
In library there was no wireload model so I have defined one.

Need to know the commands to include wireload model

Thank you

 

[vamsi1255]

Following attributes of RC can help in doing ZWLM synthesis or WLM synthesis

1) interconnect_mode
2) wireload_selection
3) force_wireload

Hope this can help you..

~vamsi

 

[spgite]

Thank you for reply..