I am doing some functional post-synthesis simulation on Modelsim and I can see lots of zero width glitches in the VCD file. Considering that it is a functional simulation, it seems to be odd.
Any idea?
Have you got any clue? I am also confused with this problem. I am using a VCD file generated by RTL simulation. And using Synopsys 'vcd2saif' command to generate saif file, in which I found a target wire has toggle counts at about 1188. I also write a perl script to count the toggle. It found more than 2700 toggles. Then I searched the VCD file and found that the target wire toggles twice at one time point sometimes.
I was using Nangate standard cell library and there was a problem in this library. In fact there was some sort of feedback in some cells and modelsim does lots of iterations on these loops. I removed them and problem solved. Are u using Nangate for synthesis?
I was using Nangate standard cell library and there was a problem in this library. In fact there was some sort of feedback in some cells and modelsim does lots of iterations on these loops. I removed them and problem solved. Are u using Nangate for synthesis?