What those fpga compilers has the vendor timing library to caculate the "primitive cell" delay by the 2 dimention ( driving , load ) . The coregen add some compiler directive like // synthesis black_box , synopsys translate_off to tell compiler to take the macro as black box , This blackbox have no timing library info , compiler ignore it and set it to 0 delay time . Look your compiler install dir/lib/<vendor device>/ to see what primitive cells timing lib provide, If you would like to see the timing report , delete those compiler directive or flatten your macro adder , report timing -from input -to output .